| /external/llvm/tools/llvm-objdump/ |
| MCFunction.cpp | 35 std::vector<MCDecodedInst> Instructions;
57 Instructions.push_back(MCDecodedInst(Index, Size, Inst));
92 std::sort(Instructions.begin(), Instructions.end());
95 unsigned ii = 0, ie = Instructions.size();
100 // Add instructions to the BB.
102 if (Instructions[ii].Address < *spi ||
103 Instructions[ii].Address >= BlockEnd)
105 BB.addInst(Instructions[ii]);
|
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.h | 67 mutable DenseMap<const Record*, CodeGenInstruction*> Instructions;
134 if (Instructions.empty()) ReadInstructions();
135 return Instructions;
140 if (Instructions.empty()) ReadInstructions();
142 Instructions.find(InstRec);
143 assert(I != Instructions.end() && "Not an instruction");
147 /// getInstructionsByEnumValue - Return all of the instructions defined by the
|
| AsmWriterEmitter.cpp | 48 /// instructions that are suitably similar to it.
62 // If this differs in the same operand as the rest of the instructions in
78 // If the operand is the same for all instructions, just print it.
81 // If this is the operand that varies between all of the instructions,
112 // instructions each case are used for. It is a comma separated string of
149 // For each entry of UniqueOperandCommands, there is a set of instructions
150 // that uses it. If the next command of all instructions in the set are
168 // Otherwise, scan to see if all of the other instructions in this command
204 // Prepend some of the instructions each case is used for onto the case val.
258 std::vector<AsmWriterInst> Instructions;
[all...] |
| CodeGenDAGPatterns.h | 11 // represent the patterns present in a .td file for instructions.
488 /// TreePattern - Represent a pattern, used for instructions, pattern
679 std::map<Record*, DAGInstruction, RecordPtrCmp> Instructions;
776 assert(Instructions.count(R) && "Unknown instruction!");
777 return Instructions.find(R)->second;
|
| /external/llvm/lib/MC/ |
| MCStreamer.cpp | 312 CurFrame->Instructions.push_back(Instruction);
323 CurFrame->Instructions.push_back(Instruction);
334 CurFrame->Instructions.push_back(Instruction);
345 CurFrame->Instructions.push_back(Instruction);
356 CurFrame->Instructions.push_back(Instruction);
367 CurFrame->Instructions.push_back(Instruction);
391 CurFrame->Instructions.push_back(Instruction);
401 CurFrame->Instructions.push_back(Instruction);
410 CurFrame->Instructions.push_back(Instruction);
493 CurFrame->Instructions.push_back(Inst)
[all...] |
| MCWin64EH.cpp | 168 uint8_t numCodes = CountOfUnwindCodes(info->Instructions);
173 MCWin64EHInstruction &frameInst = info->Instructions[info->LastFrameInst];
180 // Emit unwind instructions (in reverse order).
181 uint8_t numInst = info->Instructions.size();
183 MCWin64EHInstruction inst = info->Instructions.back();
184 info->Instructions.pop_back();
|
| MCDwarf.cpp | 662 /// EmitFrameMoves - Emit frame instructions to describe the layout of the
863 // Initial Instructions
867 std::vector<MCCFIInstruction> Instructions;
[all...] |
| /external/llvm/include/llvm/MC/ |
| MCWin64EH.h | 68 Instructions() {}
79 std::vector<MCWin64EHInstruction> Instructions;
|
| MCDwarf.h | 176 /// for a section where machine instructions have been assembled after seeing
265 Function(0), Instructions(), PersonalityEncoding(),
272 std::vector<MCCFIInstruction> Instructions;
|
| /external/oprofile/events/mips/5K/ |
| events | 16 event:0x1 counters:0 um:zero minimum:500 name:INSN_FETCHED : Instructions fetched
23 event:0xe counters:0 um:zero minimum:500 name:DUAL_ISSUED_INSNS : Dual issued instructions executed
24 event:0xf counters:0 um:zero minimum:500 name:INSNS_EXECED : Instructions executed
29 event:0x1 counters:1 um:zero minimum:500 name:INSNS_EXECED : Instructions executed
30 event:0x5 counters:1 um:zero minimum:500 name:FP_INSNS_EXECED : Floating-point instructions executed
36 event:0xf counters:1 um:zero minimum:500 name:COP2_INSNS_EXECED : COP2 instructions executed
|
| /external/llvm/lib/VMCore/ |
| Android.mk | 20 Instructions.cpp \
|
| /external/oprofile/events/mips/r10000/ |
| events | 7 event:0x01 counters:0 um:zero minimum:500 name:INSTRUCTIONS_ISSUED : Instructions issued
8 event:0x01 counters:1 um:zero minimum:500 name:INSTRUCTIONS_GRADUATED : Instructions graduated
16 event:0x05 counters:1 um:zero minimum:500 name:FP_INSTRUCTON_GRADUATED : Floating-point instructions graduated
35 event:0x0f counters:0 um:zero minimum:500 name:INSTRUCTION_GRADUATED : Instructions graduated
|
| /external/oprofile/events/mips/vr5432/ |
| events | 5 event:0x1 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS_EXECUTED : (Instructions executed)/2 and truncated
|
| /external/oprofile/events/mips/vr5500/ |
| events | 7 event:0x1 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS_EXECUTED : Instructions executed
|
| /external/oprofile/events/i386/westmere/ |
| events | 16 event:0x0b counters:0,1,2,3 um:mem_inst_retired minimum:2000000 name:MEM_INST_RETIRED : Memory instructions retired above 0 clocks (Precise Event)
19 event:0x0f counters:0,1,2,3 um:mem_uncore_retired minimum:40000 name:MEM_UNCORE_RETIRED : Load instructions retired that HIT modified data in sibling core (Precise Event)
24 event:0x17 counters:0,1,2,3 um:x01 minimum:2000000 name:INST_QUEUE_WRITES : Instructions written to instruction queue.
25 event:0x18 counters:0,1,2,3 um:x01 minimum:2000000 name:INST_DECODED : Instructions that must be decoded by decoder 0
26 event:0x19 counters:0,1,2,3 um:x01 minimum:2000000 name:TWO_UOP_INSTS_DECODED : Two Uop instructions decoded
27 event:0x1e counters:0,1,2,3 um:x01 minimum:2000000 name:INST_QUEUE_WRITE_CYCLES : Cycles instructions are written to the instruction queue
48 event:0x88 counters:0,1,2,3 um:br_inst_exec minimum:200000 name:BR_INST_EXEC : Branch instructions executed
51 event:0xa6 counters:0,1,2,3 um:x01 minimum:2000000 name:MACRO_INSTS : Macro-fused instructions decoded
63 event:0xc0 counters:0,1,2,3 um:inst_retired minimum:2000000 name:INST_RETIRED : Instructions retired (Programmable counter and Precise Event)
66 event:0xc4 counters:0,1,2,3 um:br_inst_retired minimum:200000 name:BR_INST_RETIRED : Retired branch instructions (Precise Event
[all...] |
| unit_masks | 28 0x01 cond Conditional branch instructions executed
37 0x7f any Branch instructions executed
39 0x01 conditional Retired conditional branch instructions (Precise Event)
40 0x02 near_call Retired near call instructions (Precise Event)
41 0x04 all_branches Retired branch instructions (Precise Event)
56 0x04 all_branches Mispredicted retired branch instructions (Precise Event)
91 0x01 to_fp Transitions from MMX to Floating Point instructions
92 0x02 to_mmx Transitions from Floating Point to MMX instructions
101 0x01 any_p Instructions retired (Programmable counter and Precise Event)
103 0x04 mmx Retired MMX instructions (Precise Event
[all...] |
| /external/llvm/tools/bugpoint/ |
| CrashDebugger.cpp | 19 #include "llvm/Instructions.h"
357 /// non-terminator instructions and replacing them with undef.
388 SmallPtrSet<Instruction*, 64> Instructions;
391 Instructions.insert(cast<Instruction>(VMap[Insts[i]]));
394 outs() << "Checking for crash with only " << Instructions.size();
395 if (Instructions.size() == 1)
398 outs() << " instructions: ";
404 if (!Instructions.count(Inst) && !isa<TerminatorInst>(Inst)) {
423 for (SmallPtrSet<Instruction*, 64>::const_iterator I = Instructions.begin(),
424 E = Instructions.end(); I != E; ++I
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineBasicBlock.h | 10 // Collect the sequence of machine instructions for a basic block.
63 typedef ilist<MachineInstr> Instructions;
64 Instructions Insts;
131 typedef Instructions::iterator iterator;
132 typedef Instructions::const_iterator const_iterator;
249 /// updateTerminator - Update the terminator instructions in block to account
355 // These functions delete any instructions removed.
368 /// splice - Take a block of instructions from MBB 'Other' in the range [From,
398 /// any DBG_VALUE instructions. Return UnknownLoc if there is none.
|
| /external/oprofile/events/mips/20K/ |
| events | 7 event:0x1 counters:0 um:zero minimum:500 name:INSN_ISSUED : Dispatched/issued instructions
9 event:0x3 counters:0 um:zero minimum:500 name:FP_INSNS_COMPLETED : Instructions completed in FPU datapath (computational event:instructions only)
18 event:0xc counters:0 um:zero minimum:500 name:RPS_MISSPREDICTS : JR instructions that mispredicted using the Return Prediction Stack (RPS)
|
| /external/webkit/Source/WebCore/manual-tests/inspector-wrappers/ |
| inspector-wrappers-test-utils.js | 27 function instructions(params) { function
32 "<p>Instructions:</p>" +
|
| /external/oprofile/events/mips/r12000/ |
| events | 5 event:0x1 counters:0,1,2,3 um:zero minimum:500 name:DECODED_INSTRUCTIONS : Decoded instructions
19 event:0xf counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTIONS_GRADUATED : Instructions graduated
20 event:0x10 counters:0,1,2,3 um:zero minimum:500 name:PREFETCH_INSTRUCTIONS_EXECUTED : Executed prefetch instructions
21 event:0x11 counters:0,1,2,3 um:zero minimum:500 name:PREFETCH_MISSES_IN_DCACHE : Primary data cache misses by prefetch instructions
25 event:0x15 counters:0,1,2,3 um:zero minimum:500 name:GRADUATED_FP_INSTRUCTIONS : Graduated floating point instructions
|
| /external/oprofile/events/mips/rm9000/ |
| events | 5 event:0x01 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS_ISSUED : Instructions issued
6 event:0x02 counters:0,1 um:zero minimum:500 name:FP_INSTRUCTIONS_ISSUED : Floating-point instructions issued
7 event:0x03 counters:0,1 um:zero minimum:500 name:INT_INSTRUCTIONS_ISSUED : Integer instructions issued
8 event:0x04 counters:0,1 um:zero minimum:500 name:LOAD_INSTRUCTIONS_ISSUED : Load instructions issued
9 event:0x05 counters:0,1 um:zero minimum:500 name:STORE_INSTRUCTIONS_ISSUED : Store instructions issued
21 event:0x12 counters:0,1 um:zero minimum:500 name:BRANCHES_ISSUED : Branch instructions issued
31 event:0x1c counters:0,1 um:zero minimum:500 name:CACHE_INSN_STALL_CYCLES : Stall cycles due to cache instructions
|
| /external/llvm/utils/vim/ |
| llvm.vim | 22 " Instructions.
|
| /external/oprofile/events/mips/25K/ |
| events | 7 event:0x1 counters:0,1 um:zero minimum:500 name:INSN_ISSUED : Dispatched/issued instructions
8 event:0x2 counters:0,1 um:zero minimum:500 name:FP_INSNS_ISSUED : FPU instructions issued
9 event:0x3 counters:0,1 um:zero minimum:500 name:INT_INSNS_ISSUED : Integer instructions issued
10 event:0x4 counters:0,1 um:zero minimum:500 name:LOAD_INSNS_ISSUED : Load instructions issued
11 event:0x5 counters:0,1 um:zero minimum:500 name:STORE_INSNS_ISSUED : Store instructions issued
12 event:0x6 counters:0,1 um:zero minimum:500 name:BRANCHES_JUMPS_ISSUED : Branch/Jump instructions issued
20 event:0xa counters:0,1 um:zero minimum:500 name:INSN_FP_DATAPATH_COMPLETED : Instructions completed in FPU datapath (computational instructions only)
29 event:0xf counters:0,1 um:zero minimum:500 name:JR_RPD_MISSPREDICTED : JR instructions that mispredicted using the Return Prediction Stack
50 event:0x18 counters:0,1 um:zero minimum:500 name:INSNS_FETCHED_FROM_ICACHE : Total number of instructions fetched from the I-Cach
[all...] |
| /external/llvm/test/MC/ARM/ |
| thumb-diagnostics.s | 14 @ Instructions which require v6+ for both registers to be low regs.
123 @ Out of range immediate for ADD SP instructions
|
