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Searched
refs:Lane
(Results
1 - 5
of
5
) sorted by null
/external/llvm/lib/Target/ARM/
ARMExpandPseudoInsts.cpp
90
// For quad-register load-
lane
and store-
lane
pseudo instructors, the
92
// OddDblSpc depending on the
lane
number operand.
108
unsigned char RegElts; // elements per D register; used for
lane
ops
533
// The
lane
operand is always the 3rd from last operand, before the 2
535
unsigned
Lane
= MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm();
537
// Adjust the
lane
and spacing as needed for Q registers.
538
assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-
lane
");
539
if (RegSpc == EvenDblSpc &&
Lane
>= RegElts) {
541
Lane
-= RegElts
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ARMCodeEmitter.cpp
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ARMISelLowering.cpp
[
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ARMISelDAGToDAG.cpp
224
/// SelectVLDSTLane - Select NEON load/store
lane
intrinsics. NumVecs should
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/external/jpeg/
jmemdosa.asm
4
; Copyright (C) 1992, Thomas G.
Lane
.
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