| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelDAGToDAG.cpp | 302 static bool isValidIndexedLoad(const LoadSDNode *LD) {
330 LoadSDNode *LD = cast<LoadSDNode>(N);
359 LoadSDNode *LD = cast<LoadSDNode>(N1);
|
| MSP430ISelLowering.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| SelectionDAGNodes.h | [all...] |
| SelectionDAG.h | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | 686 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) {
[all...] |
| LegalizeVectorOps.cpp | 130 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
297 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
|
| LegalizeTypes.h | 240 SDValue PromoteIntRes_LOAD(LoadSDNode *N);
314 void ExpandIntRes_LOAD (LoadSDNode *N, SDValue &Lo, SDValue &Hi);
521 SDValue ScalarizeVecRes_LOAD(LoadSDNode *N);
565 void SplitVecRes_LOAD(LoadSDNode *N, SDValue &Lo, SDValue &Hi);
649 LoadSDNode *LD);
657 LoadSDNode *LD, ISD::LoadExtType ExtType);
[all...] |
| LegalizeTypesGeneric.cpp | 208 LoadSDNode *LD = cast<LoadSDNode>(N);
|
| LegalizeVectorTypes.cpp | 59 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
185 SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
433 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
701 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
[all...] |
| SelectionDAG.cpp | 413 const LoadSDNode *LD = cast<LoadSDNode>(N);
[all...] |
| LegalizeFloatTypes.cpp | 473 LoadSDNode *L = cast<LoadSDNode>(N);
[all...] |
| TargetLowering.cpp | [all...] |
| LegalizeDAG.cpp | 496 SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
[all...] |
| LegalizeIntegerTypes.cpp | 65 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
411 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
[all...] |
| SelectionDAGBuilder.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | 196 bool MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM);
401 LoadSDNode *LD = dyn_cast<LoadSDNode>(Callee.getNode());
585 bool X86DAGToDAGISel::MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM){
770 if (!MatchLoadInAddress(cast<LoadSDNode>(N), AM))
[all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | 728 ? cast<LoadSDNode>(Op)->getAddressingMode()
764 ? cast<LoadSDNode>(Op)->getAddressingMode()
784 ? cast<LoadSDNode>(Op)->getAddressingMode()
857 ? cast<LoadSDNode>(Op)->getAddressingMode()
[all...] |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 394 LoadSDNode *LD = cast<LoadSDNode>(Op);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | [all...] |
| PPCISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | 559 LoadSDNode *LN = cast<LoadSDNode>(Op);
[all...] |
