| /external/llvm/lib/CodeGen/ |
| CallingConvLower.cpp | 88 bool CCState::CheckReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
91 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
92 MVT VT = Outs[i].VT;
93 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
102 void CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
105 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
106 MVT VT = Outs[i].VT;
107 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
120 void CCState::AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
122 unsigned NumOps = Outs.size()
[all...] |
| /external/llvm/lib/Target/PTX/ |
| PTXISelLowering.h | 61 const SmallVectorImpl<ISD::OutputArg> &Outs,
70 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| PTXISelLowering.cpp | 261 const SmallVectorImpl<ISD::OutputArg> &Outs,
271 assert(Outs.size() == 0 && "Kernel must return void.");
274 assert(Outs.size() <= 1 && "Can at most return one value.");
286 assert(Outs.size() < 2 && "Device functions can return at most one value");
288 if (Outs.size() == 1) {
298 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
299 EVT RegVT = Outs[i].VT;
348 const SmallVectorImpl<ISD::OutputArg> &Outs,
362 // The layout of the ops will be [Chain, #Ins, Ins, Callee, #Outs, Outs]
[all...] |
| /external/llvm/lib/Target/Blackfin/ |
| BlackfinISelLowering.h | 68 const SmallVectorImpl<ISD::OutputArg> &Outs,
77 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| BlackfinISelLowering.cpp | 226 const SmallVectorImpl<ISD::OutputArg> &Outs,
238 CCInfo.AnalyzeReturn(Outs, RetCC_Blackfin);
285 const SmallVectorImpl<ISD::OutputArg> &Outs,
298 CCInfo.AnalyzeCallOperands(Outs, CC_Blackfin);
|
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.h | 83 const SmallVectorImpl<ISD::OutputArg> &Outs,
92 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| SparcISelLowering.cpp | 83 const SmallVectorImpl<ISD::OutputArg> &Outs,
97 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32);
352 const SmallVectorImpl<ISD::OutputArg> &Outs,
364 CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32);
376 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
377 ISD::ArgFlagsTy Flags = Outs[i].Flags;
410 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 128 const SmallVectorImpl<ISD::OutputArg> &Outs,
157 const SmallVectorImpl<ISD::OutputArg> &Outs,
166 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| MSP430ISelLowering.cpp | 275 const SmallVectorImpl<ISD::OutputArg> &Outs,
289 Outs, OutVals, Ins, dl, DAG, InVals);
385 const SmallVectorImpl<ISD::OutputArg> &Outs,
393 if (CallConv == CallingConv::MSP430_INTR && !Outs.empty()) {
403 CCInfo.AnalyzeReturn(Outs, RetCC_MSP430);
446 &Outs,
456 CCInfo.AnalyzeCallOperands(Outs, CC_MSP430);
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.h | 97 const SmallVectorImpl<ISD::OutputArg> &Outs,
126 const SmallVectorImpl<ISD::OutputArg> &Outs,
135 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| SystemZISelLowering.cpp | 258 const SmallVectorImpl<ISD::OutputArg> &Outs,
272 Outs, OutVals, Ins, dl, DAG, InVals);
377 &Outs,
393 CCInfo.AnalyzeCallOperands(Outs, CC_SystemZ);
556 const SmallVectorImpl<ISD::OutputArg> &Outs,
568 CCInfo.AnalyzeReturn(Outs, RetCC_SystemZ);
[all...] |
| /external/llvm/lib/Target/Alpha/ |
| AlphaISelLowering.h | 127 const SmallVectorImpl<ISD::OutputArg> &Outs,
136 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| AlphaISelLowering.cpp | 232 const SmallVectorImpl<ISD::OutputArg> &Outs,
245 CCInfo.AnalyzeCallOperands(Outs, CC_Alpha);
478 const SmallVectorImpl<ISD::OutputArg> &Outs,
486 switch (Outs.size()) {
493 EVT ArgVT = Outs[0].VT;
508 EVT ArgVT = Outs[0].VT;
[all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.h | 166 const SmallVectorImpl<ISD::OutputArg> &Outs,
175 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.h | 138 const SmallVectorImpl<ISD::OutputArg> &Outs,
147 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.h | 153 const SmallVectorImpl<ISD::OutputArg> &Outs,
162 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.h | 120 const SmallVectorImpl<ISD::OutputArg> &Outs,
181 const SmallVectorImpl<ISD::OutputArg> &Outs,
190 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| XCoreISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.h | 442 const SmallVectorImpl<ISD::OutputArg> &Outs,
451 const SmallVectorImpl<ISD::OutputArg> &Outs,
457 const SmallVectorImpl<ISD::OutputArg> &Outs,
477 const SmallVectorImpl<ISD::OutputArg> &Outs,
485 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| PPCISelLowering.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| CallingConvLower.h | 201 void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
212 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.h | 456 const SmallVectorImpl<ISD::OutputArg> &Outs,
473 const SmallVectorImpl<ISD::OutputArg> &Outs,
480 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.h | 769 const SmallVectorImpl<ISD::OutputArg> &Outs,
[all...] |
| X86FastISel.cpp | 739 SmallVector<ISD::OutputArg, 4> Outs;
741 Outs, TLI);
747 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
780 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt())
786 if (Outs[0].Flags.isSExt())
791 unsigned Op = Outs[0].Flags.isZExt() ? ISD::ZERO_EXTEND :
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FunctionLoweringInfo.cpp | 67 SmallVector<ISD::OutputArg, 4> Outs;
69 Fn->getAttributes().getRetAttributes(), Outs, TLI);
72 Outs, Fn->getContext());
|
