| /external/clang/test/SemaTemplate/ |
| nested-name-spec-template.cpp | 5 template<typename T> struct Promote;
7 template<> struct Promote<short> {
11 template<> struct Promote<int> {
15 template<> struct Promote<float> {
19 Promote<short>::type *ret_intptr(int* ip) { return ip; }
20 Promote<int>::type *ret_intptr2(int* ip) { return ip; }
23 M::Promote<int>::type *ret_intptr3(int* ip) { return ip; }
24 M::template Promote<int>::type *ret_intptr4(int* ip) { return ip; } // expected-warning{{'template' keyword outside of a template}}
25 M::template Promote<int> pi; // expected-warning{{'template' keyword outside of a template}}
28 N::M::Promote<int>::type *ret_intptr5(int* ip) { return ip;
[all...] |
| /external/llvm/examples/OCaml-Kaleidoscope/Chapter7/ |
| toy.ml | 33 (* Promote allocas to registers. *)
|
| /external/llvm/lib/Target/Blackfin/ |
| BlackfinISelLowering.cpp | 56 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
57 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
58 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
68 setOperationAction(ISD::AND, MVT::i16, Promote);
69 setOperationAction(ISD::OR, MVT::i16, Promote);
70 setOperationAction(ISD::XOR, MVT::i16, Promote);
71 setOperationAction(ISD::CTPOP, MVT::i16, Promote);
72 // The expansion of CTLZ/CTTZ uses AND/OR, so we might as well promote
74 setOperationAction(ISD::CTLZ, MVT::i16, Promote);
75 setOperationAction(ISD::CTTZ, MVT::i16, Promote);
[all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | 116 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
117 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
118 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
300 setOperationAction(ISD::CTLZ , MVT::i8, Promote);
301 setOperationAction(ISD::CTLZ , MVT::i16, Promote);
325 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote);
326 setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote);
327 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
328 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote);
343 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 63 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
64 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
65 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
113 setOperationAction(ISD::CTLZ, MVT::i32, Promote);
411 // Promote the value if needed.
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetLowering.h | 92 Promote, // This operation should be executed in a larger type.
261 /// it is already legal (return 'Legal') or we need to promote it to a larger
262 /// type (return 'Promote'), or we need to expand it into multiple registers
273 /// returns the larger type to promote to. For integer types that are larger
481 assert(Action != Promote && "Can't promote condition code!");
493 /// getTypeToPromoteTo - If the action for this operation is to promote, this
494 /// method returns the ValueType to promote to.
496 assert(getOperationAction(Op, VT) == Promote &&
512 "Didn't find type to promote to!")
[all...] |
| /external/llvm/lib/Target/Alpha/ |
| AlphaISelLowering.cpp | 61 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
64 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
67 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
129 setOperationAction(ISD::SETCC, MVT::f32, Promote);
131 setOperationAction(ISD::BITCAST, MVT::f32, Promote);
263 // Promote the value if needed.
633 if (!isDouble) //Promote
783 "Unknown node to custom promote!");
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 92 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
93 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
94 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
724 // Promote the value if needed.
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 233 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
251 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
253 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
254 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
255 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
258 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
269 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
271 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
272 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
277 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 89 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
90 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
91 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
474 // Promote the value if needed.
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 231 case TargetLowering::Promote:
232 // "Promote" the operation by bitcasting
277 "Can't promote a vector with multiple results!");
|
| LegalizeDAG.cpp | 172 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 128 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
129 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
130 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 86 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
260 // We cannot do this with Promote because i64 is not a legal type.
299 // We promote all shuffles to v16i8.
300 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
303 // We promote all non-typed operations to v4i32.
304 setOperationAction(ISD::AND , VT, Promote);
306 setOperationAction(ISD::OR , VT, Promote);
308 setOperationAction(ISD::XOR , VT, Promote);
310 setOperationAction(ISD::LOAD , VT, Promote);
312 setOperationAction(ISD::SELECT, VT, Promote);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 110 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
111 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
112 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 416 // Promote the value if needed.
700 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 99 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
103 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
137 // Promote all bit-wise operations.
139 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote);
142 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote);
145 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote);
532 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
[all...] |
