| /external/qemu/ |
| ppc-dis.c | 688 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
689 #define RA NSI + 1
693 /* As above, but 0 in the RA field means zero, not r0. */
694 #define RA0 RA + 1
697 /* The RA field in the DQ form lq instruction, which has special
702 /* The RA field in a D or X form instruction which is an updating
703 load, which means that the RA field may not be zero and may not
708 /* The RA field in an lmw instruction, which has special value
713 /* The RA field in a D or X form instruction which is an updating
714 store or an updating floating point load, which means that the RA
[all...] |
| /external/qemu/tcg/ppc/ |
| tcg-target.c | 397 #define RA(r) ((r)<<16)
407 #define TAB(t,a,b) (RT(t) | RA(a) | RB(b))
408 #define SAB(s,a,b) (RS(s) | RA(a) | RB(b))
449 tcg_out32 (s, ADDI | RT (ret) | RA (0) | (arg & 0xffff));
451 tcg_out32 (s, ADDIS | RT (ret) | RA (0) | ((arg >> 16) & 0xffff));
453 tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff));
461 tcg_out32 (s, op1 | RT (ret) | RA (addr) | (offset & 0xffff));
464 tcg_out32 (s, op2 | RT (ret) | RA (addr) | RB (0));
493 tcg_out32 (s, LWZ | RT (0) | RA (reg));
494 tcg_out32 (s, MTSPR | RA (0) | CTR)
[all...] |
| /external/qemu/tcg/ppc64/ |
| tcg-target.c | 394 #define RA(r) ((r)<<16)
405 #define TAB(t,a,b) (RT(t) | RA(a) | RB(b))
406 #define SAB(s,a,b) (RS(s) | RA(a) | RB(b))
443 static void tcg_out_rld (TCGContext *s, int op, int ra, int rs, int sh, int mb)
447 tcg_out32 (s, op | RA (ra) | RS (rs) | sh | mb);
453 tcg_out32 (s, ADDI | RT (ret) | RA (0) | (arg & 0xffff));
455 tcg_out32 (s, ADDIS | RT (ret) | RA (0) | ((arg >> 16) & 0xffff));
457 tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff));
477 if (h16) tcg_out32 (s, ORIS | RS (ret) | RA (ret) | h16)
[all...] |
| /external/llvm/test/MC/MBlaze/ |
| mblaze_pattern.s | 6 # TYPE A: OPCODE RD RA RB FLAGS
|
| mblaze_shift.s | 6 # TYPE A: OPCODE RD RA RB FLAGS
|
| mblaze_fpu.s | 6 # TYPE A: OPCODE RD RA RB FLAGS
|
| mblaze_memory.s | 6 # TYPE A: OPCODE RD RA RB FLAGS
|
| mblaze_typeb.s | 6 # TYPE B: OPCODE RD RA IMMEDIATE
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| mblaze_special.s | 6 # TYPE A: OPCODE RD RA RB FLAGS
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| mblaze_typea.s | 6 # TYPE A: OPCODE RD RA RB FLAGS
|
| /external/llvm/lib/Target/MBlaze/Disassembler/ |
| MBlazeDisassembler.cpp | 526 unsigned RA = getRA(insn);
536 if (RD == UNSUPPORTED || RA == UNSUPPORTED || RB == UNSUPPORTED)
540 instr.addOperand(MCOperand::CreateReg(RA));
544 if (RD == UNSUPPORTED || RA == UNSUPPORTED || RB == UNSUPPORTED)
547 instr.addOperand(MCOperand::CreateReg(RA));
562 if (RA == UNSUPPORTED)
565 instr.addOperand(MCOperand::CreateReg(RA));
578 if (RD == UNSUPPORTED || RA == UNSUPPORTED)
581 instr.addOperand(MCOperand::CreateReg(RA));
595 if (RA == UNSUPPORTED || RB == UNSUPPORTED
[all...] |
| /external/llvm/utils/TableGen/ |
| ARMDecoderEmitter.cpp | 515 void reportRegion(bitAttr_t RA, unsigned StartBit, unsigned BitIndex,
[all...] |
| FixedLenDecoderEmitter.cpp | 353 void reportRegion(bitAttr_t RA, unsigned StartBit, unsigned BitIndex,
925 void FilterChooser::reportRegion(bitAttr_t RA, unsigned StartBit,
927 if (RA == ATTR_MIXED && AllowMixed)
929 else if (RA == ATTR_ALL_SET && !AllowMixed)
[all...] |
| /external/llvm/lib/Transforms/IPO/ |
| DeadArgumentElimination.cpp | 145 void MarkValue(const RetOrArg &RA, Liveness L,
147 void MarkLive(const RetOrArg &RA);
149 void PropagateLiveness(const RetOrArg &RA);
571 /// MarkValue - This function marks the liveness of RA depending on L. If L is
573 /// such that RA will be marked live if any use in MaybeLiveUses gets marked
575 void DAE::MarkValue(const RetOrArg &RA, Liveness L,
578 case Live: MarkLive(RA); break;
585 Uses.insert(std::make_pair(*UI, RA));
610 void DAE::MarkLive(const RetOrArg &RA) {
611 if (LiveFunctions.count(RA.F)
[all...] |
| /external/llvm/include/llvm/MC/ |
| MCRegisterInfo.h | 154 void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA,
158 RAReg = RA;
|
| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCMCTargetDesc.cpp | 46 unsigned RA = isPPC64 ? PPC::LR8 : PPC::LR;
49 InitPPCMCRegisterInfo(X, RA, Flavour, Flavour);
|
| /external/llvm/lib/Target/Mips/ |
| MipsRegisterInfo.cpp | 46 : MipsGenRegisterInfo(Mips::RA), Subtarget(ST), TII(tii) {}
49 /// Mips::RA, return the number that it corresponds to (e.g. 31).
132 case Mips::RA: case Mips::RA_64: case Mips::F31: case Mips::D31_64:
153 Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4,
159 Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4,
194 Mips::GP, Mips::SP, Mips::FP, Mips::RA, 0
|
| MipsFrameLowering.cpp | 52 // . saved RA
315 // $fp and $ra used or unused.
317 // Mark $fp and $ra as used or unused.
321 // The register allocator might determine $ra is used after seeing
322 // instruction "jr $ra", but we do not want PrologEpilogInserter to insert
323 // instructions to save/restore $ra unless there is a function call.
324 // To correct this, $ra is explicitly marked unused if there is no
327 MRI.setPhysRegUsed(Mips::RA);
329 MRI.setPhysRegUnused(Mips::RA);
|
| /external/llvm/lib/Analysis/ |
| ScalarEvolution.cpp | 479 const Argument *RA = cast<Argument>(RV);
480 unsigned LArgNo = LA->getArgNo(), RArgNo = RA->getArgNo();
514 const APInt &RA = RC->getValue()->getValue();
515 unsigned LBitWidth = LA.getBitWidth(), RBitWidth = RA.getBitWidth();
518 return LA.ult(RA) ? -1 : 1;
523 const SCEVAddRecExpr *RA = cast<SCEVAddRecExpr>(RHS);
526 const Loop *LLoop = LA->getLoop(), *RLoop = RA->getLoop();
535 unsigned LNumOps = LA->getNumOperands(), RNumOps = RA->getNumOperands();
541 long X = compare(LA->getOperand(i), RA->getOperand(i));
[all...] |
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsBaseInfo.h | 105 case Mips::RA: case Mips::RA_64: case Mips::F31: case Mips::D31_64:
|
| MipsMCTargetDesc.cpp | 44 InitMipsMCRegisterInfo(X, Mips::RA);
|
| /frameworks/base/media/libstagefright/codecs/common/include/ |
| voIndex.h | 109 _MAKE_CODEC_ID (0x240000, RA)
|
| /external/libffi/src/powerpc/ |
| darwin.S | 200 .byte 0x41 ; CIE RA Column
|
| darwin_closure.S | 259 .byte 0x41 ; CIE RA Column
|
| linux64.S | 151 .byte 0x41 # CIE RA Column
|
