/external/qemu/target-i386/ |
ops_sse_header.h | 21 #define Reg MMXReg 24 #define Reg XMMReg 31 #define dh_ctype_Reg Reg * 38 DEF_HELPER_2(glue(psrlw, SUFFIX), void, Reg, Reg) 39 DEF_HELPER_2(glue(psraw, SUFFIX), void, Reg, Reg) 40 DEF_HELPER_2(glue(psllw, SUFFIX), void, Reg, Reg) 41 DEF_HELPER_2(glue(psrld, SUFFIX), void, Reg, Reg [all...] |
/external/llvm/lib/Target/Sparc/ |
SparcMachineFunctionInfo.h | 37 void setGlobalBaseReg(unsigned Reg) { GlobalBaseReg = Reg; } 43 void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; }
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/external/llvm/lib/Target/SystemZ/ |
SystemZMachineFunctionInfo.h | 43 void setLowReg(unsigned Reg) { LowReg = Reg; } 46 void setHighReg(unsigned Reg) { HighReg = Reg; }
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SystemZInstrBuilder.h | 41 unsigned Reg; 50 Base.Reg = 0; 59 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) { 61 // values, this adds: Reg, [0, NoReg] to the instruction. 62 return MIB.addReg(Reg).addImm(0).addReg(0); 71 /// [Reg + Offset], i.e., one with no or index, but with a 76 unsigned Reg, bool isKill, int Offset) { 77 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); 81 /// [Reg + Reg] [all...] |
/external/llvm/lib/CodeGen/ |
AllocationOrder.h | 57 unsigned Reg = *Pos++; 58 if (Reg != Hint) 59 return Reg;
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MachineRegisterInfo.cpp | 46 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { 47 VRegInfo[Reg].first = RC; 51 MachineRegisterInfo::constrainRegClass(unsigned Reg, 54 const TargetRegisterClass *OldRC = getRegClass(Reg); 62 setRegClass(Reg, NewRC); 67 MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) { 69 const TargetRegisterClass *OldRC = getRegClass(Reg); 77 for (reg_nodbg_iterator I = reg_nodbg_begin(Reg), E = reg_nodbg_end(); I != E; 89 setRegClass(Reg, NewRC); 103 unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs()) [all...] |
DeadMachineInstructionElim.cpp | 72 unsigned Reg = MO.getReg(); 73 if (TargetRegisterInfo::isPhysicalRegister(Reg) ? 74 LivePhysRegs[Reg] : !MRI->use_nodbg_empty(Reg)) { 108 unsigned Reg = *LOI; 109 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 110 LivePhysRegs.set(Reg); 138 unsigned Reg = MO.getReg(); 139 if (!TargetRegisterInfo::isVirtualRegister(Reg)) 142 for (MachineRegisterInfo::use_iterator I = MRI->use_begin(Reg), [all...] |
AggressiveAntiDepBreaker.cpp | 61 unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) { 62 unsigned Node = GroupNodeIndices[Reg]; 74 for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) { 75 if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0)) 76 Regs.push_back(Reg); 83 assert(GroupNodeIndices[0] == 0 && "Reg 0 not in Group 0!"); 96 unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg) [all...] |
CriticalAntiDepBreaker.cpp | 64 unsigned Reg = *I; 65 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); 66 KillIndices[Reg] = BB->size(); 67 DefIndices[Reg] = ~0u; 70 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { 86 unsigned Reg = *I; 87 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); 88 KillIndices[Reg] = BB->size(); 89 DefIndices[Reg] = ~0u; 92 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) [all...] |
ProcessImplicitDefs.cpp | 49 unsigned Reg, unsigned OpIdx, 62 static bool isUndefCopy(MachineInstr *MI, unsigned Reg, 67 if (MO1.getReg() != Reg) 110 unsigned Reg = MI->getOperand(0).getReg(); 111 ImpDefRegs.insert(Reg); 112 if (TargetRegisterInfo::isPhysicalRegister(Reg)) { 113 for (const unsigned *SS = TRI->getSubRegisters(Reg); *SS; ++SS) 128 unsigned Reg = MI->getOperand(0).getReg(); 133 // If this was the last one, mark Reg as implicitly defined. 134 if (TargetRegisterInfo::isVirtualRegister(Reg) && MRI->def_empty(Reg) [all...] |
RegisterScavenging.cpp | 17 #define DEBUG_TYPE "reg-scavenging" 37 void RegScavenger::setUsed(unsigned Reg) { 38 RegsAvailable.reset(Reg); 40 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); 45 bool RegScavenger::isAliasUsed(unsigned Reg) const { 46 if (isUsed(Reg)) 48 for (const unsigned *R = TRI->getAliasSet(Reg); *R; ++R) 111 void RegScavenger::addRegWithSubRegs(BitVector &BV, unsigned Reg) { 112 BV.set(Reg); 113 for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++ [all...] |
LiveVariables.cpp | 126 void LiveVariables::HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB, 128 assert(MRI->getVRegDef(reg) && "Register use before def!"); 132 VarInfo& VRInfo = getVarInfo(reg); 164 if (MBB == MRI->getVRegDef(reg)->getParent()) return; 175 MarkVirtRegAliveInBlock(VRInfo, MRI->getVRegDef(reg)->getParent(), *PI); 178 void LiveVariables::HandleVirtRegDef(unsigned Reg, MachineInstr *MI) { 179 VarInfo &VRInfo = getVarInfo(Reg); 188 MachineInstr *LiveVariables::FindLastPartialDef(unsigned Reg, 193 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); 215 if (TRI->isSubRegister(Reg, DefReg)) [all...] |
/external/llvm/lib/Target/Alpha/ |
AlphaMachineFunctionInfo.h | 48 void setGlobalBaseReg(unsigned Reg) { GlobalBaseReg = Reg; } 51 void setGlobalRetAddr(unsigned Reg) { GlobalRetAddr = Reg; }
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/external/llvm/lib/Target/PTX/ |
PTXMachineFunctionInfo.h | 82 void addRetReg(unsigned Reg) { 83 if (!RegRets.count(Reg)) { 84 RegRets.insert(Reg); 88 RegNames[Reg] = name; 93 void addArgReg(unsigned Reg) { 94 RegArgs.insert(Reg); 98 RegNames[Reg] = name; 103 void addVirtualRegister(const TargetRegisterClass *TRC, unsigned Reg) { 107 if (!RegRets.count(Reg) && !RegArgs.count(Reg)) { [all...] |
PTXMFInfoExtract.cpp | 57 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); 58 const TargetRegisterClass *TRC = MRI.getRegClass(Reg); 59 MFI->addVirtualRegister(TRC, Reg);
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/external/llvm/include/llvm/CodeGen/ |
RegisterScavenging.h | 126 void setUsed(unsigned Reg); 129 bool isReserved(unsigned Reg) const { return ReservedRegs.test(Reg); } 133 bool isUsed(unsigned Reg) const { return !RegsAvailable.test(Reg); } 134 bool isUnused(unsigned Reg) const { return RegsAvailable.test(Reg); } 136 /// isAliasUsed - Is Reg or an alias currently in use? 137 bool isAliasUsed(unsigned Reg) const; 148 /// Add Reg and all its sub-registers to BV [all...] |
MachineRegisterInfo.h | 122 /// Reg are Debug instructions. 201 MachineInstr *getVRegDef(unsigned Reg) const; 207 void clearKillFlags(unsigned Reg) const; 219 const TargetRegisterClass *getRegClass(unsigned Reg) const { 220 return VRegInfo[Reg].first; 225 void setRegClass(unsigned Reg, const TargetRegisterClass *RC); 234 const TargetRegisterClass *constrainRegClass(unsigned Reg, 238 /// recomputeRegClass - Try to find a legal super-class of Reg's register 240 /// Reg. Returns true if Reg was upgraded [all...] |
LiveVariables.h | 114 /// isLiveIn - Is Reg live in to MBB? This means that Reg is live through 115 /// MBB, or it is killed in MBB. If Reg is only used by PHI instructions in 118 unsigned Reg, 164 /// HandlePhysRegKill - Add kills of Reg and its sub-registers to the 167 bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI); 169 void HandlePhysRegUse(unsigned Reg, MachineInstr *MI); 170 void HandlePhysRegDef(unsigned Reg, MachineInstr *MI, 176 MachineInstr *FindLastRefOrPartRef(unsigned Reg); 181 MachineInstr *FindLastPartialDef(unsigned Reg, [all...] |
FunctionLoweringInfo.h | 153 const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg) { 154 if (!LiveOutRegInfo.inBounds(Reg)) 157 const LiveOutInfo *LOI = &LiveOutRegInfo[Reg]; 169 const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth); 172 void AddLiveOutRegInfo(unsigned Reg, unsigned NumSignBits, 178 LiveOutRegInfo.grow(Reg); 179 LiveOutInfo &LOI = LiveOutRegInfo[Reg]; 197 unsigned Reg = It->second; 198 LiveOutRegInfo.grow(Reg); 199 LiveOutRegInfo[Reg].IsValid = false [all...] |
CallingConvLower.h | 190 bool isAllocated(unsigned Reg) const { 191 return UsedRegs[Reg/32] & (1 << (Reg&31)); 242 unsigned AllocateReg(unsigned Reg) { 243 if (isAllocated(Reg)) return 0; 244 MarkAllocated(Reg); 245 return Reg; 249 unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) { 250 if (isAllocated(Reg)) return 0; 251 MarkAllocated(Reg); [all...] |
/external/llvm/include/llvm/Target/ |
TargetRegisterInfo.h | 81 bool contains(unsigned Reg) const { 82 return MC->contains(Reg); 247 /// returns true if Reg is in the range used for stack slots. 253 static bool isStackSlot(unsigned Reg) { 254 return int(Reg) >= (1 << 30); 259 static int stackSlot2Index(unsigned Reg) { 260 assert(isStackSlot(Reg) && "Not a stack slot"); 261 return int(Reg - (1u << 30)); 273 static bool isPhysicalRegister(unsigned Reg) { 274 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first.") [all...] |
/external/llvm/lib/Target/ARM/ |
MLxExpansionPass.cpp | 63 bool hasRAWHazard(unsigned Reg, MachineInstr *MI) const; 87 unsigned Reg = MI->getOperand(1).getReg(); 88 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 92 MachineInstr *DefMI = MRI->getVRegDef(Reg); 97 Reg = DefMI->getOperand(1).getReg(); 98 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 99 DefMI = MRI->getVRegDef(Reg); 103 Reg = DefMI->getOperand(2).getReg(); 104 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 105 DefMI = MRI->getVRegDef(Reg); [all...] |
ARMBaseRegisterInfo.h | 38 static inline bool isARMArea1Register(unsigned Reg, bool isDarwin) { 40 switch (Reg) { 53 static inline bool isARMArea2Register(unsigned Reg, bool isDarwin) { 55 switch (Reg) { 64 static inline bool isARMArea3Register(unsigned Reg, bool isDarwin) { 66 switch (Reg) { 132 unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg, 135 void UpdateRegAllocHint(unsigned Reg, unsigned NewReg, 163 bool isLowRegister(unsigned Reg) const; 178 virtual bool isReservedReg(const MachineFunction &MF, unsigned Reg) const [all...] |
ARMCallingConv.h | 35 if (unsigned Reg = State.AllocateReg(RegList, 4)) 36 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 50 if (unsigned Reg = State.AllocateReg(RegList, 4)) 51 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 79 unsigned Reg = State.AllocateReg(HiRegList, ShadowRegList, 2); 80 if (Reg == 0) { 94 if (HiRegList[i] == Reg) 101 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 124 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2); 125 if (Reg == 0 [all...] |
/external/llvm/lib/Target/ |
TargetRegisterInfo.cpp | 33 if (!Reg) 35 else if (TargetRegisterInfo::isStackSlot(Reg)) 36 OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg); 37 else if (TargetRegisterInfo::isVirtualRegister(Reg)) 38 OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Reg); 39 else if (TRI && Reg < TRI->getNumRegs()) 40 OS << '%' << TRI->getName(Reg); 42 OS << "%physreg" << Reg; 55 TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, EVT VT) const { 56 assert(isPhysicalRegister(reg) && "reg must be a physical register") [all...] |