| /external/llvm/lib/CodeGen/ |
| AllocationOrder.h | 41 const RegisterClassInfo &RegClassInfo);
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| AllocationOrder.cpp | 27 const RegisterClassInfo &RegClassInfo)
28 : Begin(0), End(0), Pos(0), RCI(RegClassInfo), OwnedBegin(false) {
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| CriticalAntiDepBreaker.h | 40 const RegisterClassInfo &RegClassInfo;
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| AggressiveAntiDepBreaker.h | 122 const RegisterClassInfo &RegClassInfo;
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| RegAllocBase.h | 95 RegisterClassInfo RegClassInfo;
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| RegAllocFast.cpp | 62 RegisterClassInfo RegClassInfo;
489 !RC->contains(Hint) || !RegClassInfo.isAllocatable(Hint)))
503 ArrayRef<unsigned> AO = RegClassInfo.getOrder(RC);
765 if (RegClassInfo.isAllocatable(*I))
[all...] |
| RegisterCoalescer.cpp | 91 RegisterClassInfo RegClassInfo;
[all...] |
| CriticalAntiDepBreaker.cpp | 35 RegClassInfo(RCI),
388 ArrayRef<unsigned> Order = RegClassInfo.getOrder(RC);
535 if (!RegClassInfo.isAllocatable(AntiDepReg))
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| PostRASchedulerList.cpp | 84 RegisterClassInfo RegClassInfo;
212 RegClassInfo.runOnMachineFunction(Fn);
239 SchedulePostRATDList Scheduler(Fn, MLI, MDT, AA, RegClassInfo, AntiDepMode,
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| RegAllocBasic.cpp | 236 RegClassInfo.runOnMachineFunction(vrm.getMachineFunction());
339 RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front());
489 RegClassInfo.getOrder(MRI->getRegClass(VirtReg.reg));
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| AggressiveAntiDepBreaker.cpp | 124 RegClassInfo(RCI),
623 ArrayRef<unsigned> Order = RegClassInfo.getOrder(SuperRC);
642 if (!RegClassInfo.isAllocatable(NewSuperReg)) continue;
823 if (!RegClassInfo.isAllocatable(AntiDepReg)) {
[all...] |
| RegAllocGreedy.cpp | 637 if (unsigned CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg))
[all...] |
| RegAllocLinearScan.cpp | 145 RegisterClassInfo RegClassInfo;
362 ArrayRef<unsigned> O = RegClassInfo.getOrder(RC);
516 RegClassInfo.runOnMachineFunction(fn);
[all...] |
