| /external/llvm/include/llvm/CodeGen/ |
| RegisterScavenging.h | 141 void setUsed(BitVector &Regs) {
142 RegsAvailable &= ~Regs;
144 void setUnused(BitVector &Regs) {
145 RegsAvailable |= Regs;
|
| CallingConvLower.h | 232 unsigned getFirstUnallocated(const unsigned *Regs, unsigned NumRegs) const {
234 if (!isAllocated(Regs[i]))
259 unsigned AllocateReg(const unsigned *Regs, unsigned NumRegs) {
260 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs);
265 unsigned Reg = Regs[FirstUnalloc];
271 unsigned AllocateReg(const unsigned *Regs, const unsigned *ShadowRegs,
273 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs);
278 unsigned Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc];
|
| MachineRegisterInfo.h | 293 void addPhysRegsUsed(const BitVector &Regs) { UsedPhysRegs |= Regs; }
|
| /external/llvm/utils/TableGen/ |
| RegisterInfoEmitter.cpp | 99 const std::vector<CodeGenRegister*> &Regs,
108 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
109 Record *Reg = Regs[i]->TheDef;
162 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
163 Record *Reg = Regs[i]->TheDef;
262 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
265 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
266 const CodeGenRegister *Reg = Regs[i];
282 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
283 const CodeGenRegister &Reg = *Regs[i]
[all...] |
| RegisterInfoEmitter.h | 52 const std::vector<CodeGenRegister*> &Regs, bool isCtor);
|
| CodeGenTarget.cpp | 175 const std::vector<CodeGenRegister*> &Regs = getRegBank().getRegisters();
176 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
177 if (Regs[i]->TheDef->getValueAsString("AsmName") == Name)
178 return Regs[i];
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| CodeGenRegisters.cpp | 523 std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register");
524 std::sort(Regs.begin(), Regs.end(), LessRecord());
525 Registers.reserve(Regs.size());
527 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
528 getReg(Regs[i]);
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| AsmMatcherEmitter.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMFrameLowering.cpp | 551 SmallVector<std::pair<unsigned,bool>, 4> Regs;
579 Regs.push_back(std::make_pair(Reg, isKill));
582 if (Regs.empty())
584 if (Regs.size() > 1 || StrOpc== 0) {
588 for (unsigned i = 0, e = Regs.size(); i < e; ++i)
589 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second));
590 } else if (Regs.size() == 1) {
593 .addReg(Regs[0].first, getKillRegState(Regs[0].second)
[all...] |
| ARMLoadStoreOptimizer.cpp | 93 DebugLoc dl, SmallVector<std::pair<unsigned, bool>, 8> &Regs);
286 /// registers in Regs as the register operands that would be loaded / stored.
294 SmallVector<std::pair<unsigned, bool>, 8> &Regs) {
296 unsigned NumRegs = Regs.size();
326 NewBase = Regs[NumRegs-1].first;
359 MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef)
360 | getKillRegState(Regs[i].second));
395 SmallVector<std::pair<unsigned, bool>, 8> Regs;
401 Regs.push_back(std::make_pair(Reg, isKill));
408 Pred, PredReg, Scratch, dl, Regs))
[all...] |
| Thumb2SizeReduction.cpp | 189 for (const unsigned *Regs = MCID.ImplicitDefs; *Regs; ++Regs)
190 if (*Regs == ARM::CPSR)
|
| /external/llvm/lib/CodeGen/ |
| AggressiveAntiDepBreaker.h | 97 std::vector<unsigned> &Regs,
|
| AggressiveAntiDepBreaker.cpp | 71 std::vector<unsigned> &Regs,
76 Regs.push_back(Reg);
157 // In a return block, examine the function live-out regs.
169 // In a non-return block, examine the live-in regs of all successors.
558 std::vector<unsigned> Regs;
559 State->GetGroupRegs(AntiDepGroupIndex, Regs, &RegRefs);
560 assert(Regs.size() > 0 && "Empty register group!");
561 if (Regs.size() == 0)
571 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
572 unsigned Reg = Regs[i]
[all...] |
| LocalStackSlotAllocation.cpp | 201 lookupCandidateBaseReg(const SmallVector<std::pair<unsigned, int64_t>, 8> &Regs,
207 unsigned e = Regs.size();
209 RegOffset = Regs[i];
|
| /external/llvm/lib/Transforms/Scalar/ |
| LoopStrengthReduce.cpp | 704 SmallPtrSet<const SCEV *, 16> &Regs,
715 SmallPtrSet<const SCEV *, 16> &Regs,
719 SmallPtrSet<const SCEV *, 16> &Regs,
728 SmallPtrSet<const SCEV *, 16> &Regs,
761 if (!Regs.count(AR->getStart())) {
762 RateRegister(AR->getStart(), Regs, L, SE, DT);
771 if (!Regs.count(AR->getOperand(1))) {
772 RateRegister(AR->getOperand(1), Regs, L, SE, DT);
796 SmallPtrSet<const SCEV *, 16> &Regs,
799 if (Regs.insert(Reg)
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGBuilder.cpp | 568 /// Regs - This list holds the registers assigned to the values.
572 SmallVector<unsigned, 4> Regs;
576 RegsForValue(const SmallVector<unsigned, 4> ®s,
578 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
589 Regs.push_back(Reg + i);
609 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
664 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT)
[all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
