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  /external/llvm/lib/Target/SystemZ/
SystemZRegisterInfo.cpp 54 BitVector Reserved(getNumRegs());
59 Reserved.set(SystemZ::R11D);
60 Reserved.set(SystemZ::R11W);
61 Reserved.set(SystemZ::R10P);
62 Reserved.set(SystemZ::R10Q);
65 Reserved.set(SystemZ::R14D);
66 Reserved.set(SystemZ::R15D);
67 Reserved.set(SystemZ::R14W);
68 Reserved.set(SystemZ::R15W);
69 Reserved.set(SystemZ::R14P)
    [all...]
  /external/llvm/lib/Target/PTX/
PTXRegisterInfo.h 42 BitVector Reserved(getNumRegs());
43 return Reserved; // reserve no regs
  /external/llvm/lib/Target/Sparc/
SparcRegisterInfo.cpp 43 BitVector Reserved(getNumRegs());
44 // FIXME: G1 reserved for now for large imm generation by frame code.
45 Reserved.set(SP::G1);
46 Reserved.set(SP::G2);
47 Reserved.set(SP::G3);
48 Reserved.set(SP::G4);
49 Reserved.set(SP::O6);
50 Reserved.set(SP::I6);
51 Reserved.set(SP::I7);
52 Reserved.set(SP::G0)
    [all...]
  /external/llvm/lib/Target/MBlaze/
MBlazeRegisterInfo.cpp 72 BitVector Reserved(getNumRegs());
73 Reserved.set(MBlaze::R0);
74 Reserved.set(MBlaze::R1);
75 Reserved.set(MBlaze::R2);
76 Reserved.set(MBlaze::R13);
77 Reserved.set(MBlaze::R14);
78 Reserved.set(MBlaze::R15);
79 Reserved.set(MBlaze::R16);
80 Reserved.set(MBlaze::R17);
81 Reserved.set(MBlaze::R18)
    [all...]
  /development/tools/yuv420sp2rgb/
Android.mk 1 # Copyright 2005 Google Inc. All Rights Reserved.
  /external/llvm/lib/Target/Blackfin/
BlackfinRegisterInfo.cpp 57 BitVector Reserved(getNumRegs());
58 Reserved.set(AZ);
59 Reserved.set(AN);
60 Reserved.set(AQ);
61 Reserved.set(AC0);
62 Reserved.set(AC1);
63 Reserved.set(AV0);
64 Reserved.set(AV0S);
65 Reserved.set(AV1);
66 Reserved.set(AV1S)
    [all...]
  /external/llvm/lib/Target/MSP430/
MSP430RegisterInfo.cpp 78 BitVector Reserved(getNumRegs());
81 // Mark 4 special registers with subregisters as reserved.
82 Reserved.set(MSP430::PCB);
83 Reserved.set(MSP430::SPB);
84 Reserved.set(MSP430::SRB);
85 Reserved.set(MSP430::CGB);
86 Reserved.set(MSP430::PCW);
87 Reserved.set(MSP430::SPW);
88 Reserved.set(MSP430::SRW);
89 Reserved.set(MSP430::CGW)
    [all...]
  /external/icu4c/test/testdata/
tstfiles.mk 1 # Copyright (C) 2007, International Business Machines Corporation and others. All Rights Reserved.
  /external/llvm/lib/CodeGen/
RegisterClassInfo.h 11 // information about target register classes. Callee saved and reserved
57 // Reserved registers in the current MF.
58 BitVector Reserved;
85 /// contains no reserved registers, and registers that alias callee saved
110 /// isReserved - Returns true when PhysReg is a reserved register.
112 /// Reserved registers may belong to an allocatable register class, but the
116 return Reserved.test(PhysReg);
120 /// register class and it hasn't been reserved.
RegisterClassInfo.cpp 11 // information about target register classes. Callee saved and reserved
56 // Different reserved registers?
58 if (RR != Reserved)
60 Reserved = RR;
67 /// compute - Compute the preferred allocation order for RC with reserved
73 // Raw register count, including all reserved regs.
87 // Remove reserved registers from the allocation order.
88 if (Reserved.test(PhysReg))
  /development/tools/etc1tool/
Android.mk 1 # Copyright 2009 Google Inc. All Rights Reserved.
  /external/icu4c/
configure.mk 1 # Copyright (c) 2008-2010, International Business Machines Corporation and others. All Rights Reserved.
  /external/icu4c/test/perf/unisetperf/draft/
contperf.bat 2 rem others. All Rights Reserved.
span16perf.bat 2 rem others. All Rights Reserved.
span8perf.bat 2 rem others. All Rights Reserved.
  /external/icu4c/test/perf/utrie2perf/
utrie2perf.bat 2 rem All Rights Reserved.
  /external/llvm/lib/Target/Alpha/
AlphaRegisterInfo.cpp 72 BitVector Reserved(getNumRegs());
73 Reserved.set(Alpha::R15);
74 Reserved.set(Alpha::R29);
75 Reserved.set(Alpha::R30);
76 Reserved.set(Alpha::R31);
77 return Reserved;
  /external/llvm/lib/Target/XCore/
XCoreRegisterInfo.cpp 87 BitVector Reserved(getNumRegs());
90 Reserved.set(XCore::CP);
91 Reserved.set(XCore::DP);
92 Reserved.set(XCore::SP);
93 Reserved.set(XCore::LR);
95 Reserved.set(XCore::R10);
97 return Reserved;
  /external/llvm/lib/Target/PowerPC/
PPCRegisterInfo.cpp 221 BitVector Reserved(getNumRegs());
225 Reserved.set(PPC::R0);
226 Reserved.set(PPC::R1);
227 Reserved.set(PPC::LR);
228 Reserved.set(PPC::LR8);
229 Reserved.set(PPC::RM);
233 Reserved.set(PPC::R2); // System-reserved register
234 Reserved.set(PPC::R13); // Small Data Area pointer register
240 Reserved.set(PPC::R2)
    [all...]
  /external/llvm/lib/Target/X86/
X86RegisterInfo.cpp 390 BitVector Reserved(getNumRegs());
393 // Set the stack-pointer register and its aliases as reserved.
394 Reserved.set(X86::RSP);
395 Reserved.set(X86::ESP);
396 Reserved.set(X86::SP);
397 Reserved.set(X86::SPL);
399 // Set the instruction pointer register and its aliases as reserved.
400 Reserved.set(X86::RIP);
401 Reserved.set(X86::EIP);
402 Reserved.set(X86::IP)
    [all...]
  /external/freetype/include/freetype/
tttables.h 159 /* Reserved :: 8~reserved bytes. */
196 FT_Short Reserved[4];
281 /* This value is `reserved' in vmtx */
284 /* Reserved :: 8~reserved bytes. */
322 FT_Short Reserved[4];
457 FT_Byte Reserved;
    [all...]
  /external/icu4c/data/translit/
trnsfiles.mk 2 # * Corporation and others. All Rights Reserved.
  /external/llvm/lib/Target/
TargetRegisterInfo.cpp 93 // Mask out the reserved registers
94 BitVector Reserved = getReservedRegs(MF);
95 Allocatable &= Reserved.flip();
  /external/ppp/pppd/
chap_ms.h 4 * Copyright (c) 1995 Eric Rosenquist. All rights reserved.
78 u_char Reserved[8]; /* Must be zero */
  /external/llvm/lib/Target/Mips/
MipsRegisterInfo.cpp 202 BitVector Reserved(getNumRegs());
206 Reserved.set(*Reg);
210 Reserved.set(*Reg);
215 Reserved.set(*Reg);
221 Reserved.set(*Reg);
225 Reserved.set(*Reg);
228 return Reserved;

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