| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeTypes.h | 77 bool IgnoreNodeResults(SDNode *N) const {
116 SmallVector<SDNode*, 128> Worklist;
131 void NoteDeletion(SDNode *Old, SDNode *New) {
139 SDNode *AnalyzeNewNode(SDNode *N);
141 void ExpungeNode(SDNode *N);
149 bool CustomLowerNode(SDNode *N, EVT VT, bool LegalizeResult);
150 bool CustomWidenLowerNode(SDNode *N, EVT VT);
155 SDValue DisintegrateMERGE_VALUES(SDNode *N, unsigned ResNo)
[all...] |
| SDNodeOrdering.h | 1 //===-- llvm/CodeGen/SDNodeOrdering.h - SDNode Ordering ---------*- C++ -*-===//
21 class SDNode;
24 /// SDNode that roughly corresponds to the ordering of the original LLVM
29 DenseMap<const SDNode*, unsigned> OrderMap;
36 void add(const SDNode *Node, unsigned O) {
39 void remove(const SDNode *Node) {
40 DenseMap<const SDNode*, unsigned>::iterator Itr = OrderMap.find(Node);
47 unsigned getOrder(const SDNode *Node) {
|
| InstrEmitter.h | 41 void EmitCopyFromReg(SDNode *Node, unsigned ResNo,
48 unsigned getDstOfOnlyCopyToRegUse(SDNode *Node,
51 void CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
88 void EmitSubregNode(SDNode *Node, DenseMap<SDValue, unsigned> &VRBaseMap,
95 void EmitCopyToRegClassNode(SDNode *Node,
100 void EmitRegSequence(SDNode *Node, DenseMap<SDValue, unsigned> &VRBaseMap,
106 static unsigned CountResults(SDNode *Node);
112 static unsigned CountOperands(SDNode *Node);
121 void EmitNode(SDNode *Node, bool IsClone, bool IsCloned,
140 void EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned
[all...] |
| ScheduleDAGSDNodes.h | 1 //===---- ScheduleDAGSDNodes.h - SDNode Scheduling --------------*- C++ -*-===//
11 // scheduling for an SDNode-based dependency graph.
22 /// ScheduleDAGSDNodes - A ScheduleDAG for scheduling SDNode-based DAGs.
32 /// SDNode-based scheduling graphs do not use SDep::Anti or SDep::Output
52 static bool isPassiveNode(SDNode *Node) {
70 SUnit *NewSUnit(SDNode *N);
103 virtual void ComputeOperandLatency(SDNode *Def, SDNode *Use,
124 const SDNode *Node;
138 const SDNode *GetNode() const
[all...] |
| SelectionDAGPrinter.cpp | 46 return ((const SDNode *) Node)->getNumValues();
50 return ((const SDNode *) Node)->getValueType(i).getEVTString();
55 return itostr(I - SDNodeIterator::begin((SDNode *) Node));
71 SDNode *TargetNode = *I;
85 static bool hasNodeAddressLabel(const SDNode *Node,
105 static std::string getSimpleNodeLabel(const SDNode *Node,
114 std::string getNodeLabel(const SDNode *Node, const SelectionDAG *Graph);
115 static std::string getNodeAttributes(const SDNode *N,
139 std::string DOTGraphTraits<SelectionDAG*>::getNodeLabel(const SDNode *Node,
179 void SelectionDAG::setGraphAttrs(const SDNode *N, const char *Attrs)
[all...] |
| SDNodeDbgValue.h | 24 class SDNode;
33 SDNODE = 0, // value is the result of an expression
41 SDNode *Node; // valid for expressions
54 SDDbgValue(MDNode *mdP, SDNode *N, unsigned R, uint64_t off, DebugLoc dl,
57 kind = SDNODE;
83 // Returns the SDNode* for a register ref
84 SDNode *getSDNode() { assert (kind==SDNODE); return u.s.Node; }
87 unsigned getResNo() { assert (kind==SDNODE); return u.s.ResNo; }
106 // property. A SDDbgValue is invalid if the SDNode that produces the value i
[all...] |
| ScheduleDAGSDNodes.cpp | 60 SUnit *ScheduleDAGSDNodes::NewSUnit(SDNode *N) {
102 static void CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op,
126 static void AddGlue(SDNode *N, SDValue Glue, bool AddGlue, SelectionDAG *DAG) {
128 SDNode *GlueDestNode = Glue.getNode();
171 void ScheduleDAGSDNodes::ClusterNeighboringLoads(SDNode *Node) {
172 SDNode *Chain = 0;
181 SmallPtrSet<SDNode*, 16> Visited;
183 DenseMap<long long, SDNode*> O2SMap; // Map from offset to SDNode
[all...] |
| LegalizeFloatTypes.cpp | 45 void DAGTypeLegalizer::SoftenFloatResult(SDNode *N, unsigned ResNo) {
107 SDValue DAGTypeLegalizer::SoftenFloatRes_BITCAST(SDNode *N) {
111 SDValue DAGTypeLegalizer::SoftenFloatRes_MERGE_VALUES(SDNode *N,
117 SDValue DAGTypeLegalizer::SoftenFloatRes_BUILD_PAIR(SDNode *N) {
132 SDValue DAGTypeLegalizer::SoftenFloatRes_EXTRACT_VECTOR_ELT(SDNode *N) {
139 SDValue DAGTypeLegalizer::SoftenFloatRes_FABS(SDNode *N) {
151 SDValue DAGTypeLegalizer::SoftenFloatRes_FADD(SDNode *N) {
163 SDValue DAGTypeLegalizer::SoftenFloatRes_FCEIL(SDNode *N) {
174 SDValue DAGTypeLegalizer::SoftenFloatRes_FCOPYSIGN(SDNode *N) {
216 SDValue DAGTypeLegalizer::SoftenFloatRes_FCOS(SDNode *N)
[all...] |
| SelectionDAGISel.cpp | 181 SDNode *Node) const {
425 SmallPtrSet<SDNode*, 128> VisitedNodes;
426 SmallVector<SDNode*, 128> Worklist;
435 SDNode *N = Worklist.pop_back_val();
650 SDNode *Node = --ISelPosition;
657 SDNode *ResNode = Select(Node);
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| SelectionDAGISel.h | 76 virtual SDNode *Select(SDNode *N) = 0;
91 virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
97 static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
191 virtual void NodeDeleted(SDNode *N, SDNode *E) {
197 virtual void NodeUpdated(SDNode *N) {}
216 void ReplaceUses(SDNode *F, SDNode *T)
[all...] |
| SelectionDAG.h | 11 // SDNode class and subclasses.
40 template<> struct ilist_traits<SDNode> : public ilist_default_traits<SDNode> {
42 mutable ilist_half_node<SDNode> Sentinel;
44 SDNode *createSentinel() const {
45 return static_cast<SDNode*>(&Sentinel);
47 static void destroySentinel(SDNode *) {}
49 SDNode *provideInitialHead() const { return createSentinel(); }
50 SDNode *ensureHead(SDNode*) const { return createSentinel();
[all...] |
| SelectionDAGNodes.h | 10 // This file declares the SDNode class and derived classes, which are used to
44 class SDNode;
51 void checkForCycles(const SDNode *N);
67 bool isBuildVectorAllOnes(const SDNode *N);
71 bool isBuildVectorAllZeros(const SDNode *N);
76 bool isScalarToVector(const SDNode *N);
91 SDNode *Node; // The node defining the value we are using.
95 SDValue(SDNode *node, unsigned resno) : Node(node), ResNo(resno) {}
97 /// get the index which selects a specific result in the SDNode
100 /// get the SDNode which holds the desired resul
[all...] |
| Analysis.h | 29 class SDNode;
87 bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
|
| /external/llvm/lib/Target/PTX/ |
| PTXISelDAGToDAG.cpp | 36 SDNode *Select(SDNode *Node);
50 SDNode *SelectBRCOND(SDNode *Node);
52 SDNode *SelectREADPARAM(SDNode *Node);
53 SDNode *SelectWRITEPARAM(SDNode *Node);
54 SDNode *SelectFrameIndex(SDNode *Node)
[all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.h | 64 SDValue get_vec_u18imm(SDNode *N, SelectionDAG &DAG,
66 SDValue get_vec_i16imm(SDNode *N, SelectionDAG &DAG,
68 SDValue get_vec_i10imm(SDNode *N, SelectionDAG &DAG,
70 SDValue get_vec_i8imm(SDNode *N, SelectionDAG &DAG,
72 SDValue get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG,
74 SDValue get_v4i32_imm(SDNode *N, SelectionDAG &DAG);
75 SDValue get_v2i64_imm(SDNode *N, SelectionDAG &DAG);
118 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
121 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
|
| SPUISelDAGToDAG.cpp | 179 SDNode *emitBuildVector(SDNode *bvNode) {
197 if (SDNode *N = Select(bvNode))
221 if (SDNode *N = SelectCode(Dummy.getValue().getNode()))
228 SDNode *Select(SDNode *N);
231 SDNode *SelectSHLi64(SDNode *N, EVT OpVT);
234 SDNode *SelectSRLi64(SDNode *N, EVT OpVT)
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelDAGToDAG.cpp | 118 SDNode *Select(SDNode *N);
119 SDNode *SelectIndexedLoad(SDNode *Op);
120 SDNode *SelectIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2,
329 SDNode *MSP430DAGToDAGISel::SelectIndexedLoad(SDNode *N) {
353 SDNode *MSP430DAGToDAGISel::SelectIndexedBinOp(SDNode *Op
[all...] |
| /external/llvm/lib/Target/Blackfin/ |
| BlackfinISelDAGToDAG.cpp | 53 SDNode *Select(SDNode *N);
77 SDNode *BlackfinDAGToDAGISel::Select(SDNode *N) {
128 SDNode *N,
133 SDNode *New = DAG.UpdateNodeOperands(N, ops.data(), ops.size());
150 for (SDNode::use_iterator UI = NI->use_begin(); !UI.atEnd(); ++UI) {
168 SDNode *Copy =
|
| /external/llvm/lib/Target/Mips/ |
| MipsISelDAGToDAG.cpp | 83 SDNode *getGlobalBaseReg();
84 SDNode *Select(SDNode *N);
105 SDNode *MipsDAGToDAGISel::getGlobalBaseReg() {
189 SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
232 SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, dl, VT, Ops, 2);
233 SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, dl, VT,
251 SDNode *Mul = CurDAG->getMachineNode(Op, dl, MVT::Glue, Op1, Op2);
254 SDNode *Lo = CurDAG->getMachineNode(Mips::MFLO, dl, MVT::i32
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelDAGToDAG.cpp | 81 SDNode *getGlobalBaseReg();
82 SDNode *Select(SDNode *N);
100 static bool isIntS32Immediate(SDNode *N, int32_t &Imm) {
182 SDNode *MBlazeDAGToDAGISel::getGlobalBaseReg() {
189 SDNode* MBlazeDAGToDAGISel::Select(SDNode *Node) {
250 SDNode *ResNode = CurDAG->getMachineNode(MBlaze::BRLID, dl, MVT::Other,
262 SDNode *ResNode = SelectCode(Node);
|
| /external/llvm/lib/Target/Alpha/ |
| AlphaISelDAGToDAG.cpp | 145 SDNode *Select(SDNode *N);
184 SDNode *getGlobalBaseReg();
185 SDNode *getGlobalRetAddr();
186 void SelectCALL(SDNode *Op);
194 SDNode *AlphaDAGToDAGISel::getGlobalBaseReg() {
201 SDNode *AlphaDAGToDAGISel::getGlobalRetAddr() {
208 SDNode *AlphaDAGToDAGISel::Select(SDNode *N) {
241 SDNode *CNode
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelDAGToDAG.cpp | 49 SDNode *Select(SDNode *N);
50 SDNode *SelectBRIND(SDNode *N);
58 inline bool immMskBitp(SDNode *inN) const {
154 SDNode *XCoreDAGToDAGISel::Select(SDNode *N) {
172 SDNode *node = CurDAG->getMachineNode(XCore::LDWCP_lru6, dl, MVT::i32,
224 if (SDNode *ResNode = SelectBRIND(N))
259 SDNode *XCoreDAGToDAGISel::SelectBRIND(SDNode *N)
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | 29 class SDNode;
469 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
470 SmallVectorImpl<SDNode*> &NewNodes) const {
491 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
504 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
648 SDNode *DefNode, unsigned DefIdx,
649 SDNode *UseNode, unsigned UseIdx) const;
659 SDNode *Node) const
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | 92 SDNode *Select(SDNode *N);
95 bool hasNoVMLxHazardUse(SDNode *N) const;
137 bool SelectAddrMode2OffsetReg(SDNode *Op, SDValue N,
139 bool SelectAddrMode2OffsetImm(SDNode *Op, SDValue N,
141 bool SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N,
146 bool SelectAddrMode3Offset(SDNode *Op, SDValue N,
150 bool SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,SDValue &Align);
151 bool SelectAddrMode6Offset(SDNode *Op, SDValue N, SDValue &Offset);
178 bool SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelDAGToDAG.cpp | 44 SDNode *Select(SDNode *N);
64 SDNode* getGlobalBaseReg();
68 SDNode* SparcDAGToDAGISel::getGlobalBaseReg() {
137 SDNode *SparcDAGToDAGISel::Select(SDNode *N) {
175 SDNode *Mul = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::Glue,
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