| /external/llvm/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | 153 // SDValue.getNode() == 0 - No change was made
154 // SDValue.getNode() == N - N was replaced, is dead and has been handled.
442 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
447 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
461 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
470 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
476 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
483 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
487 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(),
526 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()
[all...] |
| LegalizeVectorOps.cpp | 108 for (unsigned i = 0, e = Op.getNode()->getNumValues(); i != e; ++i)
119 SDNode* Node = Op.getNode();
127 SDValue(DAG.UpdateNodeOperands(Op.getNode(), Ops.data(), Ops.size()), 0);
130 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
139 StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
239 if (Tmp1.getNode()) {
255 Result = DAG.UnrollVectorOp(Op.getNode());
276 assert(Op.getNode()->getNumValues() == 1 &&
284 Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Op.getOperand(j));
289 Op = DAG.getNode(Op.getOpcode(), dl, NVT, &Operands[0], Operands.size())
[all...] |
| LegalizeDAG.cpp | 277 Node = Node->getOperand(0).getNode();
320 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest,
399 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
438 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
440 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
461 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
476 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
483 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
491 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
511 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad)
[all...] |
| LegalizeIntegerTypes.cpp | 142 if (Res.getNode())
155 return DAG.getNode(ISD::AssertSext, N->getDebugLoc(),
162 return DAG.getNode(ISD::AssertZext, N->getDebugLoc(),
222 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp));
226 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
233 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
247 InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
251 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp);
256 return DAG.getNode(ISD::BITCAST, dl, OutVT, GetWidenedVector(InOp));
259 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT
[all...] |
| LegalizeTypesGeneric.cpp | 57 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
58 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
64 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
65 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
71 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
72 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
77 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
78 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
85 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
87 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp
[all...] |
| SelectionDAGBuilder.cpp | 130 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
131 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
137 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
151 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
152 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
155 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
156 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
163 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
164 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
167 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi)
[all...] |
| LegalizeVectorTypes.cpp | 121 if (R.getNode())
128 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
140 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
156 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(),
164 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(),
170 return DAG.getNode(ISD::FPOWI, N->getDebugLoc(),
181 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, Op);
209 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), DestVT, Op);
216 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), EltVT,
226 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, InOp)
[all...] |
| LegalizeTypes.cpp | 44 // folding that occurs when using the DAG.getNode operators. Secondly, a new
102 assert(NewVal.getNode()->getNodeId() != NewNode &&
273 if (IgnoreNodeResults(N->getOperand(i).getNode()))
398 // the checking loop below. Implicit folding by the DAG.getNode operators and
420 if (!IgnoreNodeResults(I->getOperand(i).getNode()) &&
480 if (Op.getNode()->getNodeId() == Processed)
526 Val.setNode(AnalyzeNewNode(Val.getNode()));
527 if (Val.getNode()->getNodeId() == Processed)
562 assert(I->first.getNode() != N);
568 assert(I->first.getNode() != N)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | 86 return IndexReg.getNode() != 0 || Base_Reg.getNode() != 0;
94 dyn_cast_or_null<RegisterSDNode>(Base_Reg.getNode()))
107 if (Base_Reg.getNode() != 0)
108 Base_Reg.getNode()->dump();
114 if (IndexReg.getNode() != 0)
115 IndexReg.getNode()->dump();
257 if (AM.Segment.getNode())
365 if (Chain.getNode() == Load.getNode())
[all...] |
| X86ISelLowering.cpp | 93 return DAG.getNode(ISD::UNDEF, dl, ResultVT);
108 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
144 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
[all...] |
| /external/apache-harmony/prefs/src/test/java/org/apache/harmony/prefs/tests/java/util/prefs/ |
| PreferenceChangeEventTest.java | 46 assertSame(Preferences.userRoot(), event.getNode());
52 assertSame(Preferences.userRoot(), event.getNode());
58 assertSame(Preferences.userRoot(), event.getNode());
64 assertSame(Preferences.userRoot(), event.getNode());
73 assertSame(Preferences.userRoot(), event.getNode());
|
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | 84 Op.getNode()->getValueType(0).getTypeForEVT(*DAG.getContext());
607 basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
627 rotate = DAG.getNode(ISD::ADD, dl, PtrVT,
646 basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Op0, Op1);
652 basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Op0, Op1);
655 basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
662 rotate = DAG.getNode(ISD::ADD, dl, PtrVT,
679 result = DAG.getNode(SPUISD::ROTBYTES_LEFT, dl, MVT::i128,
686 result = DAG.getNode(SPUISD::VEC2PREFSLOT, dl, InVT,
687 DAG.getNode(ISD::BITCAST, dl, vecVT, result))
[all...] |
| SPUISelDAGToDAG.cpp | 124 return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
139 return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
186 (SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i16).getNode() != 0)) ||
188 ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
189 (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
190 (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
191 (SPU::get_v4i32_imm(bvNode, *CurDAG).getNode() != 0))) ||
193 ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) ||
194 (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) ||
195 (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i64).getNode() != 0))))
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelDAGToDAG.cpp | 59 if (Base.Reg.getNode() != 0)
60 Base.Reg.getNode()->dump();
69 if (IndexReg.getNode() != 0) IndexReg.getNode()->dump();
210 AM.Base.Reg.getNode() == 0) {
227 if (MatchAddress(N.getNode()->getOperand(0), AM, is12Bit, Depth+1)) {
232 if (AM.IndexReg.getNode() || AM.isRI) {
240 (!AM.Base.Reg.getNode() || AM.Base.Reg.getNode()->hasOneUse())) {
246 SDValue RHS = N.getNode()->getOperand(1)
[all...] |
| /external/llvm/lib/Target/PTX/ |
| PTXSelectionDAGInfo.cpp | 70 DAG.getNode(ISD::ADD, dl, PointerType, Src,
77 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
82 DAG.getNode(ISD::ADD, dl, PointerType, Dst,
88 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
109 DAG.getNode(ISD::ADD, dl, PointerType, Src,
117 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
131 DAG.getNode(ISD::ADD, dl, PointerType, Dst,
138 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
|
| /external/apache-xml/src/main/java/org/apache/xml/dtm/ref/ |
| DTMNodeIterator.java | 140 return dtm_iter.getDTM(handle).getNode(handle);
166 return dtm_iter.getDTM(handle).getNode(handle);
184 return dtm_iter.getDTM(handle).getNode(handle);
|
| /external/llvm/include/llvm/CodeGen/PBQP/ |
| Graph.h | 111 NodeEntry& getNode(NodeItr nItr) { return *nItr; }
112 const NodeEntry& getNode(ConstNodeItr nItr) const { return *nItr; }
128 NodeEntry &n1 = getNode(ne.getNode1());
129 NodeEntry &n2 = getNode(ne.getNode2());
195 Vector& getNodeCosts(NodeItr nItr) { return getNode(nItr).getCosts(); }
201 return getNode(nItr).getCosts();
209 void setNodeData(NodeItr nItr, void *data) { getNode(nItr).setData(data); }
214 void* getNodeData(NodeItr nItr) { return getNode(nItr).getData(); }
244 return getNode(nItr).getDegree();
269 return getNode(nItr).edgesBegin()
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMSelectionDAGInfo.cpp | 67 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
74 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
79 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
85 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
106 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
114 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
128 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
135 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
170 Src = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src);
172 Src = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Src)
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 183 case ISD::SUB: return ExpandADDSUB(Op.getNode(), DAG);
217 SDValue Cond = DAG.getNode(ISD::SETCC, dl, MVT::i32, Op.getOperand(2),
219 return DAG.getNode(ISD::SELECT, dl, MVT::i32, Cond, Op.getOperand(0),
230 return DAG.getNode(XCoreISD::PCRelativeWrapper, dl, MVT::i32, GA);
240 return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, GA);
242 return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, GA);
254 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
292 SDValue offset = DAG.getNode(ISD::MUL, dl, MVT::i32, BuildGetId(DAG, dl),
294 return DAG.getNode(ISD::ADD, dl, MVT::i32, base, offset);
305 return DAG.getNode(XCoreISD::PCRelativeWrapper, DL, getPointerTy(), Result)
[all...] |
| /external/llvm/include/llvm/Analysis/ |
| PostDominators.h | 50 return DT->getNode(BB);
53 inline DomTreeNode *getNode(BasicBlock *BB) const {
54 return DT->getNode(BB);
|
| RegionIterator.h | 62 NodeType* getNode() const{ return Node.getPointer(); }
71 succ = getNode()->getParent()->getNode(BB);
79 return getNode()->template getNodeAs<Region>()->getExit();
84 return getNode()->getParent()->getExit() == BB;
135 while (BItor != succ_end(getNode()->getEntry())
149 assert(getNode()->getParent() == I.getNode()->getParent()
294 return R->getNode(R->getEntry()); \
|
| /external/apache-xml/src/main/java/org/apache/xalan/transformer/ |
| XalanTransformState.java | 69 m_currentNode = dtm.getNode(currentNodeHandle);
93 return dtm.getNode(m_transformer.getCurrentNode());
124 return dtm.getNode(m_matchedNode);
127 return dtm.getNode(m_transformer.getMatchedNode());
|
| /libcore/luni/src/main/java/javax/xml/transform/dom/ |
| DOMSource.java | 108 public Node getNode() {
|
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 138 if (Flag.getNode())
139 return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain,
141 return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain,
207 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
208 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue);
216 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg);
218 Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg,
220 Arg = DAG.getNode(ISD::TRUNCATE, dl, VA.getLocVT(), Arg);
262 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
263 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue)
[all...] |
| /external/llvm/lib/Target/Alpha/ |
| AlphaISelLowering.cpp | 201 SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, MVT::i64, JTI,
203 SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, MVT::i64, JTI, Hi);
268 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
271 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
274 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
285 if (StackPtr.getNode() == 0)
288 SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
300 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
325 if (InFlag.getNode())
328 Chain = DAG.getNode(AlphaISD::CALL, dl, NodeTys, &Ops[0], Ops.size())
[all...] |
