| /external/v8/src/mips/ |
| disasm-mips.cc | 848 case LWL:
849 Format(instr, "lwl 'rt, 'imm16s('rs)");
|
| assembler-mips.h | 628 void lwl(Register rd, const MemOperand& rs);
[all...] |
| assembler-mips.cc | 1371 void Assembler::lwl(Register rd, const MemOperand& rs) { function in class:v8::internal::Assembler
[all...] |
| /external/webkit/Source/JavaScriptCore/assembler/ |
| MacroAssemblerMIPS.h | 538 lwl dest, address.offset(addrTemp)
541 lwl dest, address.offset+3(addrTemp)
547 m_assembler.lwl(dest, addrTempRegister, address.offset);
550 m_assembler.lwl(dest, addrTempRegister, address.offset + 3);
575 m_assembler.lwl(dest, addrTempRegister, 0);
578 m_assembler.lwl(dest, addrTempRegister, 3);
[all...] |
| MIPSAssembler.h | 427 void lwl(RegisterID rt, RegisterID rs, int offset) function in class:JSC::MIPSAssembler
|
| /external/v8/test/cctest/ |
| test-assembler-mips.cc | 832 // Test LWL, LWR, SWL and SWR instructions.
860 // Test all combinations of LWL and vAddr.
862 __ lwl(t0, MemOperand(a0, OFFSET_OF(T, mem_init)) );
866 __ lwl(t1, MemOperand(a0, OFFSET_OF(T, mem_init) + 1) );
870 __ lwl(t2, MemOperand(a0, OFFSET_OF(T, mem_init) + 2) );
874 __ lwl(t3, MemOperand(a0, OFFSET_OF(T, mem_init) + 3) );
[all...] |
