| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMAddressingModes.h | 32 rrx enumerator in enum:llvm::ARM_AM::ShiftOpc
51 case ARM_AM::rrx: return "rrx";
104 // reg [asr|lsl|lsr|ror|rrx] reg
105 // reg [asr|lsl|lsr|ror|rrx] imm
|
| ARMMCCodeEmitter.cpp | 186 case ARM_AM::rrx: return 3;
[all...] |
| /external/llvm/test/MC/ARM/ |
| basic-arm-instructions.s | 66 adc r4, r5, r6, rrx
80 adc r4, r5, rrx
85 adc r4, r5, rrx
104 @ CHECK: adc r4, r5, r6, rrx @ encoding: [0x66,0x40,0xa5,0xe0]
117 @ CHECK: adc r4, r4, r5, rrx @ encoding: [0x65,0x40,0xa4,0xe0]
122 @ CHECK: adc r4, r4, r5, rrx @ encoding: [0x65,0x40,0xa4,0xe0]
159 add r4, r5, r6, rrx
173 add r4, r5, rrx
186 @ CHECK: add r4, r5, r6, rrx @ encoding: [0x66,0x40,0x85,0xe0]
200 @ CHECK: add r4, r4, r5, rrx @ encoding: [0x65,0x40,0x84,0xe0
[all...] |
| basic-thumb2-instructions.s | [all...] |
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 91 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
251 if (ShOpc == ARM_AM::rrx)
268 if (ShOpc == ARM_AM::rrx)
832 if (ShOpc != ARM_AM::rrx)
|
| /frameworks/base/media/libstagefright/codecs/avc/enc/src/ |
| sad_inline.h | 212 ANDS x7, mask, x7, rrx; local
360 __asm__ volatile("EOR %1, %2, %0\n\tADDS %0, %2, %0\n\tEOR %1, %1, %0\n\tANDS %1, %3, %1, rrx\n\tRSB %1, %1, %1, lsl #8\n\tSUB %0, %0, %1, asr #7\n\tEOR %0, %0, %1, asr #7": "=r"(src1), "=&r"(x7): "r"(src2), "r"(mask));
|
| /frameworks/base/media/libstagefright/codecs/m4v_h263/enc/src/ |
| sad_inline.h | 217 ANDS x7, mask, x7, rrx; local
401 "ands %1, %4, %1,rrx\n\t"
|
| /external/llvm/lib/Target/ARM/ |
| ARMCodeEmitter.cpp | 422 case ARM_AM::rrx: return 3;
881 case ARM::RRX:
882 // rrx
[all...] |
| ARMExpandPseudoInsts.cpp | [all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | [all...] |
