| /external/llvm/lib/Target/ARM/ |
| ARMRegisterInfo.cpp | 19 ARMRegisterInfo::ARMRegisterInfo(const ARMBaseInstrInfo &tii,
21 : ARMBaseRegisterInfo(tii, sti) {
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| ARMRegisterInfo.h | 28 ARMRegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &STI);
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| ARMHazardRecognizer.h | 27 const ARMBaseInstrInfo &TII;
38 const ARMBaseInstrInfo &tii,
42 ScoreboardHazardRecognizer(ItinData, DAG, "post-RA-sched"), TII(tii),
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| Thumb2RegisterInfo.cpp | 27 Thumb2RegisterInfo::Thumb2RegisterInfo(const ARMBaseInstrInfo &tii,
29 : ARMBaseRegisterInfo(tii, sti) {
48 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2LDRpci))
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| Thumb2RegisterInfo.h | 29 Thumb2RegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &STI);
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| Thumb1RegisterInfo.h | 29 Thumb1RegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &STI);
56 const ARMBaseInstrInfo &TII) const;
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| /external/llvm/lib/Target/PTX/ |
| PTXRegisterInfo.cpp | 29 const TargetInstrInfo &tii)
31 : PTXGenRegisterInfo(0), TII(tii) {
60 //MachineInstr* MI2 = BuildMI(MBB, II, dl, TII.get(PTX::LOAD_LOCAL_F32))
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| PTXRegisterInfo.h | 29 const TargetInstrInfo &TII;
33 const TargetInstrInfo &tii);
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| /external/llvm/lib/CodeGen/ |
| RegisterCoalescer.h | 29 const TargetInstrInfo &TII;
59 CoalescerPair(const TargetInstrInfo &tii, const TargetRegisterInfo &tri)
60 : TII(tii), TRI(tri), DstReg(0), SrcReg(0), SubIdx(0),
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| LiveRangeEdit.cpp | 46 const TargetInstrInfo &tii,
50 if (!tii.isTriviallyReMaterializable(DefMI, aa))
57 const TargetInstrInfo &tii,
67 checkRematerializable(VNI, DefMI, tii, aa);
73 const TargetInstrInfo &tii,
76 scanRemattable(lis, tii, aa);
147 const TargetInstrInfo &tii,
151 tii.reMaterialize(MBB, MI, DestReg, 0, RM.OrigMI, tri);
166 const TargetInstrInfo &TII) {
199 MachineInstr *FoldMI = TII.foldMemoryOperand(UseMI, Ops, DefMI)
[all...] |
| Spiller.cpp | 59 const TargetInstrInfo *tii; member in class:__anon8169::SpillerBase
69 tii = mf.getTarget().getInstrInfo();
139 tii->loadRegFromStackSlot(*mi->getParent(), miItr, newVReg, ss, trc,
153 tii->storeRegToStackSlot(*mi->getParent(), llvm::next(miItr), newVReg,
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| /external/llvm/lib/Target/Alpha/ |
| AlphaRegisterInfo.h | 28 const TargetInstrInfo &TII;
30 AlphaRegisterInfo(const TargetInstrInfo &tii);
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| /external/llvm/lib/Target/MBlaze/ |
| MBlazeRegisterInfo.h | 40 const TargetInstrInfo &TII;
43 const TargetInstrInfo &tii);
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| MBlazeRegisterInfo.cpp | 45 MBlazeRegisterInfo(const MBlazeSubtarget &ST, const TargetInstrInfo &tii)
46 : MBlazeGenRegisterInfo(MBlaze::R15), Subtarget(ST), TII(tii) {}
107 New = BuildMI(MF,Old->getDebugLoc(),TII.get(MBlaze::ADDIK),MBlaze::R1)
111 New = BuildMI(MF,Old->getDebugLoc(),TII.get(MBlaze::ADDIK),MBlaze::R1)
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| /external/llvm/lib/Target/Mips/ |
| MipsRegisterInfo.h | 30 const TargetInstrInfo &TII;
32 MipsRegisterInfo(const MipsSubtarget &Subtarget, const TargetInstrInfo &tii);
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| /external/llvm/lib/Target/Sparc/ |
| SparcRegisterInfo.h | 30 const TargetInstrInfo &TII;
32 SparcRegisterInfo(SparcSubtarget &st, const TargetInstrInfo &tii);
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| /external/llvm/lib/Target/SystemZ/ |
| SystemZRegisterInfo.h | 30 const SystemZInstrInfo &TII;
32 SystemZRegisterInfo(SystemZTargetMachine &tm, const SystemZInstrInfo &tii);
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| SystemZRegisterInfo.cpp | 35 const SystemZInstrInfo &tii)
36 : SystemZGenRegisterInfo(0), TM(tm), TII(tii) {
124 MI.setDesc(TII.getMemoryInstr(MI.getOpcode(), Offset));
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| /external/llvm/lib/Target/Blackfin/ |
| BlackfinRegisterInfo.h | 31 const TargetInstrInfo &TII;
33 BlackfinRegisterInfo(BlackfinSubtarget &st, const TargetInstrInfo &tii);
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| /external/llvm/lib/Target/CellSPU/ |
| SPURegisterInfo.h | 31 const TargetInstrInfo &TII;
37 SPURegisterInfo(const SPUSubtarget &subtarget, const TargetInstrInfo &tii);
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| SPUHazardRecognizers.cpp | 33 SPUHazardRecognizer::SPUHazardRecognizer(const TargetInstrInfo &tii) :
34 TII(tii),
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| /external/llvm/lib/Target/MSP430/ |
| MSP430RegisterInfo.h | 30 const TargetInstrInfo &TII;
36 MSP430RegisterInfo(MSP430TargetMachine &tm, const TargetInstrInfo &tii);
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| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.h | 32 const TargetInstrInfo &TII;
34 PPCRegisterInfo(const PPCSubtarget &SubTarget, const TargetInstrInfo &tii);
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| /external/llvm/lib/Target/X86/ |
| X86RegisterInfo.h | 30 const TargetInstrInfo &TII;
54 X86RegisterInfo(X86TargetMachine &tm, const TargetInstrInfo &tii);
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| /external/llvm/lib/Target/XCore/ |
| XCoreRegisterInfo.h | 28 const TargetInstrInfo &TII;
43 XCoreRegisterInfo(const TargetInstrInfo &tii);
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