| /external/llvm/lib/Transforms/Utils/ |
| DemoteRegToStack.cpp | 11 // virtual register computed by an Instruction and replaces it with a slot in
13 // AllocaInst inserted. After this function is called on an instruction, we are
14 // guaranteed that the only user of the instruction is a store that is
27 /// Instruction and replaces it with a slot in the stack frame, allocated via
32 AllocaInst* llvm::DemoteRegToStack(Instruction &I, bool VolatileLoads,
33 Instruction *AllocaPoint) {
50 // Change all of the users of the instruction to read from the stack slot
53 Instruction *U = cast<Instruction>(I.use_back());
77 // If this is a normal instruction, just insert a load
[all...] |
| AddrModeMatcher.cpp | 17 #include "llvm/Instruction.h"
101 if (isa<Instruction>(ScaleReg) && // not a constant expr.
107 // this instruction.
109 AddrModeInsts.push_back(cast<Instruction>(ScaleReg));
123 static bool MightBeFoldableInst(Instruction *I) {
125 case Instruction::BitCast:
130 case Instruction::PtrToInt:
133 case Instruction::IntToPtr:
136 case Instruction::Add:
138 case Instruction::Mul
[all...] |
| /external/proguard/src/proguard/optimize/peephole/ |
| GotoCommonCodeReplacer.java | 27 import proguard.classfile.instruction.*;
28 import proguard.classfile.instruction.visitor.InstructionVisitor;
94 public void visitAnyInstruction(Clazz clazz, Method method, CodeAttribute codeAttribute, int offset, Instruction instruction) {}
99 // Check if the instruction is an unconditional goto instruction that
126 codeAttributeEditor.replaceInstruction( deleteOffset, (Instruction)null);
127 codeAttributeEditor.insertBeforeInstruction(deleteOffset, (Instruction)null);
128 codeAttributeEditor.insertAfterInstruction( deleteOffset, (Instruction)null);
134 // Redirect the goto instruction, if it is still necessary
[all...] |
| /external/webkit/Source/JavaScriptCore/bytecode/ |
| Instruction.h | 57 // Structure used by op_get_by_id_self_list and op_get_by_id_proto_list instruction to hold data off the main opcode stream.
125 struct Instruction {
126 Instruction(Opcode opcode)
136 Instruction(int operand)
144 Instruction(JSGlobalData& globalData, JSCell* owner, Structure* structure)
149 Instruction(JSGlobalData& globalData, JSCell* owner, StructureChain* structureChain)
154 Instruction(JSGlobalData& globalData, JSCell* owner, JSCell* jsCell)
159 Instruction(PolymorphicAccessStructureList* polymorphicStructures) { u.polymorphicStructures = polymorphicStructures; }
160 Instruction(PropertySlot::GetValueFunc getterFunc) { u.getterFunc = getterFunc; }
173 Instruction(StructureChain*)
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| Sink.cpp | 55 bool SinkInstruction(Instruction *I, SmallPtrSet<Instruction *, 8> &Stores);
56 bool AllUsesDominatedByBlock(Instruction *Inst, BasicBlock *BB) const;
71 bool Sinking::AllUsesDominatedByBlock(Instruction *Inst,
80 Instruction *UseInst = cast<Instruction>(*I);
132 SmallPtrSet<Instruction *, 8> Stores;
134 Instruction *Inst = I; // The instruction to sink.
148 // If we just processed the first instruction in the block, we're done
[all...] |
| /external/llvm/utils/TableGen/ |
| X86DisassemblerTables.h | 46 /// The instruction information table
49 /// True if there are primary decode conflicts in the instruction set
52 /// emitOneID - Emits a table entry for a single instruction entry, at the
56 /// of the instruction as listed in the LLVM tables.
60 /// @param id - The unique ID of the instruction to print.
170 /// emitInstructionInfo - Prints the instruction specifier table, which has
171 /// one entry for each instruction, and contains name and operand
190 /// nnnn is the ID of the current instruction (0-based). This table
192 /// 0xnn is the lowest possible opcode for the current instruction, used for
196 /// @param o - The output stream to which the instruction table should be
[all...] |
| /external/llvm/test/MC/ARM/ |
| diagnostics.s | 6 @ 's' bit on an instruction that can't accept it.
8 @ CHECK-ERRORS: error: instruction 'mls' can not set flags,
54 @ CHECK-ERRORS: error: invalid operand for instruction
64 @ CHECK-ERRORS: error: invalid operand for instruction
65 @ CHECK-ERRORS: error: invalid operand for instruction
66 @ CHECK-ERRORS: error: invalid operand for instruction
67 @ CHECK-ERRORS: error: invalid operand for instruction
73 @ CHECK-ERRORS: error: invalid operand for instruction
74 @ CHECK-ERRORS: error: invalid operand for instruction
85 @ CHECK-ERRORS: error: invalid operand for instruction
[all...] |
| /build/core/combo/arch/arm/ |
| armv4t.mk | 5 # it's mostly an obsoleted instruction set architecture (only available
7 # code in assembler source since the bx (branch and exchange) instruction is
|
| /dalvik/dexgen/src/com/android/dexgen/dex/code/ |
| OutputCollector.java | 31 * {@code non-null;} the associated finisher (which holds the instruction
57 * Adds an instruction to the output.
59 * @param insn {@code non-null;} the instruction to add
68 * indicated instruction really is a reversible branch.
71 * {@code 0} is the most recently added instruction,
72 * {@code 1} is the instruction before that, etc.
80 * Adds an instruction to the output suffix.
82 * @param insn {@code non-null;} the instruction to add
|
| /dalvik/dx/src/com/android/dx/dex/code/ |
| OutputCollector.java | 33 * {@code non-null;} the associated finisher (which holds the instruction
60 * Adds an instruction to the output.
62 * @param insn {@code non-null;} the instruction to add
71 * indicated instruction really is a reversible branch.
74 * {@code 0} is the most recently added instruction,
75 * {@code 1} is the instruction before that, etc.
83 * Adds an instruction to the output suffix.
85 * @param insn {@code non-null;} the instruction to add
|
| /dalvik/vm/compiler/template/armv5te/ |
| TEMPLATE_MONITOR_ENTER_DEBUG.S | 9 * r4 - the Dalvik PC of the following instruction.
21 sub r0, r4, #2 @ roll dPC back to this monitor instruction
|
| /dalvik/vm/mterp/arm-vfp/ |
| fbinop2addr.S | 3 * an "instr" line that specifies an instruction that performs
21 GOTO_OPCODE(ip) @ jump to next instruction
|
| fbinopWide.S | 3 * Provide an "instr" line that specifies an instruction that performs
23 GOTO_OPCODE(ip) @ jump to next instruction
|
| fbinopWide2addr.S | 3 * an "instr" line that specifies an instruction that performs
22 GOTO_OPCODE(ip) @ jump to next instruction
|
| funop.S | 3 * line that specifies an instruction that performs "s1 = op s0".
18 GOTO_OPCODE(ip) @ jump to next instruction
|
| funopNarrower.S | 3 * "instr" line that specifies an instruction that performs "s0 = op d0".
18 GOTO_OPCODE(ip) @ jump to next instruction
|
| funopWider.S | 3 * "instr" line that specifies an instruction that performs "d0 = op s0".
18 GOTO_OPCODE(ip) @ jump to next instruction
|
| /dalvik/vm/mterp/armv5te/ |
| alt_stub.S | 2 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
3 * any interesting requests and then jump to the real instruction
|
| /dalvik/vm/mterp/armv6t2/ |
| unopWider.S | 4 * that specifies an instruction that performs "result = op r0", where
19 GOTO_OPCODE(ip) @ jump to next instruction
|
| /dalvik/vm/mterp/x86/ |
| OP_MONITOR_EXIT.S | 8 * if they happened at the following instruction. See the Dalvik
9 * instruction spec.
|
| alt_stub.S | 2 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
3 * any interesting requests and then jump to the real instruction
|
| binop.S | 4 * specifies an instruction that performs "result = eax op (rFP,%ecx,4)".
5 * This could be an x86 instruction or a function call. (If the result
|
| binopLit16.S | 4 * that specifies an instruction that performs "result = eax op ecx".
5 * This could be an x86 instruction or a function call. (If the result
|
| binopLit8.S | 4 * that specifies an instruction that performs "result = eax op ecx".
5 * This could be an x86 instruction or a function call. (If the result
|
| /external/llvm/include/llvm/MC/ |
| MCFixup.h | 1 //===-- llvm/MC/MCFixup.h - Instruction Relocation and Patching -*- C++ -*-===//
38 /// sequence (e.g., an encoded instruction) which requires assemble- or run-
41 /// Fixups are used any time the target instruction encoder needs to represent
42 /// some value in an instruction which is not yet concrete. The encoder will
43 /// encode the instruction assuming the value is 0, and emit a fixup which
54 /// an instruction or an assembler directive.
57 /// The byte index of start of the relocation inside the encoded instruction.
61 /// determine how the operand value should be encoded into the instruction.
|
