| /external/kernel-headers/original/linux/ |
| smp.h | 21 * main cross-CPU interfaces, handles INIT, TLB flush, STOP, etc.
64 #define MSG_INVALIDATE_TLB 0x0001 /* Remote processor TLB invalidate */
|
| /external/oprofile/events/mips/20K/ |
| events | 10 event:0x4 counters:0 um:zero minimum:500 name:TLB_REFILLS_TAKEN : Taken TLB refill exceptions
13 event:0x7 counters:0 um:zero minimum:500 name:JTLB_EXCEPTIONS : Taken Joint-TLB exceptions
|
| /external/kernel-headers/original/asm-arm/ |
| procinfo.h | 40 struct cpu_tlb_fns *tlb; member in struct:proc_info_list
|
| /external/oprofile/events/mips/rm7000/ |
| events | 17 event:0x0d counters:0,1 um:zero minimum:500 name:DTLB_MISSES : Data TLB misses
18 event:0x0e counters:0,1 um:zero minimum:500 name:ITLB_MISSES : Instruction TLB misses
19 event:0x0f counters:0,1 um:zero minimum:500 name:JTLB_INSTRUCTION_MISSES : Joint TLB instruction misses
20 event:0x10 counters:0,1 um:zero minimum:500 name:JTLB_DATA_MISSES : Joint TLB data misses
|
| /external/oprofile/events/mips/vr5500/ |
| events | 13 event:0x7 counters:0,1 um:zero minimum:500 name:JTLB_REFILLS : TLB refill
|
| /external/oprofile/events/arm/armv7-ca9/ |
| events | 13 event:0x61 counters:1,2,3,4,5,6 um:zero minimum:500 name:DC_DEP_STALL : Number of cycles where CPU has some instructions that it cannot issue to any pipeline and the LSU has at least one pending linefill request but no pending TLB requests
31 event:0x82 counters:1,2,3,4,5,6 um:zero minimum:500 name:STALL_INS_TLB : Number of cycles where CPU is stalled because of main TLB misses on requests issued by the instruction side
32 event:0x83 counters:1,2,3,4,5,6 um:zero minimum:500 name:STALL_DATA_TLB : Number of cycles where CPU is stalled because of main TLB misses on requests issued by the data side
33 event:0x84 counters:1,2,3,4,5,6 um:zero minimum:500 name:STALL_INS_UTLB : Number of cycles where CPU is stalled because of micro TLB misses on the instruction side
34 event:0x85 counters:1,2,3,4,5,6 um:zero minimum:500 name:STALL_DATA_ULTB : Number of cycles where CPU is stalled because of micro TLB misses on the data side
|
| /external/clang/lib/Sema/ |
| TreeTransform.h | 301 QualType TransformType(TypeLocBuilder &TLB, TypeLoc TL);
491 QualType Transform##CLASS##Type(TypeLocBuilder &TLB, CLASS##TypeLoc T);
498 TransformTemplateSpecializationType(TypeLocBuilder &TLB,
503 TransformDependentTemplateSpecializationType(TypeLocBuilder &TLB,
509 TransformDependentTemplateSpecializationType(TypeLocBuilder &TLB,
535 QualType TransformReferenceType(TypeLocBuilder &TLB, ReferenceTypeLoc TL);
[all...] |
| /external/oprofile/events/arm/armv7-common/ |
| events | 6 event:0x02 counters:1,2,3,4,5,6 um:zero minimum:500 name:ITLB_MISS : Instruction fetch misses from TLB
9 event:0x05 counters:1,2,3,4,5,6 um:zero minimum:500 name:DTLB_REFILL : Data R/W that causes a TLB refill
|
| /external/oprofile/events/avr32/ |
| events | 6 event:0x03 counters:1,2 um:zero minimum:500 name:ITLB_MISS : number of Instruction TLB misses
7 event:0x04 counters:1,2 um:zero minimum:500 name:DTLB_MISS : number of Data TLB misses
|
| /external/oprofile/events/mips/24K/ |
| events | 24 event:0x5 counters:0 um:zero minimum:500 name:ITLB_ACCESSES : 5-0 Instruction micro-TLB accesses
25 event:0x6 counters:0 um:zero minimum:500 name:DTLB_ACCESSES : 6-0 Data micro-TLB accesses
26 event:0x7 counters:0 um:zero minimum:500 name:JTLB_INSN_ACCESSES : 7-0 Joint TLB instruction accesses
27 event:0x8 counters:0 um:zero minimum:500 name:JTLB_DATA_ACCESSES : 8-0 Joint TLB data (non-instruction) accesses
89 event:0x405 counters:1 um:zero minimum:500 name:ITLB_MISSES : 5-1 Instruction micro-TLB misses
90 event:0x406 counters:1 um:zero minimum:500 name:DTLB_MISSES : 6-1 Data micro-TLB misses
91 event:0x407 counters:1 um:zero minimum:500 name:JTLB_INSN_MISSES : 7-1 Joint TLB instruction misses
92 event:0x408 counters:1 um:zero minimum:500 name:JTLB_DATA_MISSES : 8-1 Joint TLB data (non-instruction) misses
|
| /external/oprofile/events/mips/loongson2/ |
| events | 16 event:0x0d counters:0 um:zero minimum:300 name:TLB_REFILL : TLB refill exception
31 event:0x1c counters:1 um:zero minimum:500 name:ITLB_MISSES : Instruction TLB misses
|
| /external/qemu/memcheck/ |
| memcheck_api.h | 69 * 1 Address should be invalidated in TLB cache, in order to ensure that
85 * 1 Address should be invalidated in TLB cache, in order to ensure that
|
| /external/icu4c/samples/break/ |
| break.vcproj | 48 TypeLibraryName=".\x86\Release/break.tlb"
141 TypeLibraryName=".\x64\Release/break.tlb"
235 TypeLibraryName=".\x86\Debug/break.tlb"
329 TypeLibraryName=".\x64\Debug/break.tlb"
|
| /external/icu4c/samples/cal/ |
| cal.vcproj | 44 TypeLibraryName=".\x86\Release/cal.tlb"
134 TypeLibraryName=".\x64\Release/cal.tlb"
224 TypeLibraryName=".\x86\Debug/cal.tlb"
316 TypeLibraryName=".\x64\Debug/cal.tlb"
|
| /external/icu4c/samples/case/ |
| case.vcproj | 44 TypeLibraryName=".\x86\Debug/case.tlb"
135 TypeLibraryName=".\x64\Debug/case.tlb"
226 TypeLibraryName=".\x86\Release/case.tlb"
316 TypeLibraryName=".\x64\Release/case.tlb"
|
| case.vcxproj | 82 <TypeLibraryName>.\x86\Debug/case.tlb</TypeLibraryName>
122 <TypeLibraryName>.\x64\Debug/case.tlb</TypeLibraryName>
162 <TypeLibraryName>.\x86\Release/case.tlb</TypeLibraryName>
201 <TypeLibraryName>.\x64\Release/case.tlb</TypeLibraryName>
|
| /external/icu4c/samples/coll/ |
| coll.vcproj | 44 TypeLibraryName=".\x86\Release/coll.tlb"
134 TypeLibraryName=".\x64\Release/coll.tlb"
224 TypeLibraryName=".\x86\Debug/coll.tlb"
316 TypeLibraryName=".\x64\Debug/coll.tlb"
|
| coll.vcxproj | 82 <TypeLibraryName>.\x86\Release/coll.tlb</TypeLibraryName>
121 <TypeLibraryName>.\x64\Release/coll.tlb</TypeLibraryName>
160 <TypeLibraryName>.\x86\Debug/coll.tlb</TypeLibraryName>
201 <TypeLibraryName>.\x64\Debug/coll.tlb</TypeLibraryName>
|
| /external/icu4c/samples/date/ |
| date.vcproj | 44 TypeLibraryName=".\x86\Release/date.tlb"
134 TypeLibraryName=".\x64\Release/date.tlb"
224 TypeLibraryName=".\x86\Debug/date.tlb"
315 TypeLibraryName=".\x64\Debug/date.tlb"
|
| /external/icu4c/samples/datefmt/ |
| datefmt.vcproj | 44 TypeLibraryName=".\x86\Debug/datefmt.tlb"
135 TypeLibraryName=".\x64\Debug/datefmt.tlb"
226 TypeLibraryName=".\x86\Release/datefmt.tlb"
316 TypeLibraryName=".\x64\Release/datefmt.tlb"
|
| datefmt.vcxproj | 82 <TypeLibraryName>.\x86\Debug/datefmt.tlb</TypeLibraryName>
122 <TypeLibraryName>.\x64\Debug/datefmt.tlb</TypeLibraryName>
162 <TypeLibraryName>.\x86\Release/datefmt.tlb</TypeLibraryName>
201 <TypeLibraryName>.\x64\Release/datefmt.tlb</TypeLibraryName>
|
| /external/icu4c/samples/msgfmt/ |
| msgfmt.vcproj | 44 TypeLibraryName=".\x86\Release/msgfmt.tlb"
134 TypeLibraryName=".\x64\Release/msgfmt.tlb"
224 TypeLibraryName=".\x86\Debug/msgfmt.tlb"
315 TypeLibraryName=".\x64\Debug/msgfmt.tlb"
|
| msgfmt.vcxproj | 82 <TypeLibraryName>.\x86\Release/msgfmt.tlb</TypeLibraryName>
121 <TypeLibraryName>.\x64\Release/msgfmt.tlb</TypeLibraryName>
160 <TypeLibraryName>.\x86\Debug/msgfmt.tlb</TypeLibraryName>
200 <TypeLibraryName>.\x64\Debug/msgfmt.tlb</TypeLibraryName>
|
| /external/icu4c/samples/numfmt/ |
| numfmt.vcproj | 44 TypeLibraryName=".\x86\Debug/numfmt.tlb"
135 TypeLibraryName=".\x64\Debug/numfmt.tlb"
226 TypeLibraryName=".\x86\Release/numfmt.tlb"
316 TypeLibraryName=".\x64\Release/numfmt.tlb"
|
| numfmt.vcxproj | 82 <TypeLibraryName>.\x86\Debug/numfmt.tlb</TypeLibraryName>
122 <TypeLibraryName>.\x64\Debug/numfmt.tlb</TypeLibraryName>
162 <TypeLibraryName>.\x86\Release/numfmt.tlb</TypeLibraryName>
201 <TypeLibraryName>.\x64\Release/numfmt.tlb</TypeLibraryName>
|
