| /external/icu4c/tools/toolutil/ |
| toolutil.vcxproj | 86 <TypeLibraryName>.\..\..\..\lib\icutu.tlb</TypeLibraryName>
129 <TypeLibraryName>.\..\..\..\lib\icutud.tlb</TypeLibraryName>
172 <TypeLibraryName>.\..\..\..\lib64\icutu.tlb</TypeLibraryName>
213 <TypeLibraryName>.\..\..\..\lib64\icutud.tlb</TypeLibraryName>
|
| /external/kernel-headers/original/asm-x86/ |
| fixmap_32.h | 51 * TLB entries of such buffers will not be flushed across
|
| /external/oprofile/events/arm/armv6/ |
| events | 16 event:0x0f counters:0,1 um:zero minimum:500 name:TLB_MISS : Main TLB miss
|
| /external/oprofile/events/arm/mpcore/ |
| events | 19 event:0x10 counters:0,1 um:zero minimum:500 name:TLB_MISS : main TLB miss
|
| /external/oprofile/events/mips/5K/ |
| events | 32 event:0x7 counters:1 um:zero minimum:500 name:TLB_MISS_EXCEPTIONS : TLB miss exceptions
|
| /prebuilt/linux-x86/toolchain/i686-linux-glibc2.7-4.4.3/sysroot/usr/include/linux/ |
| if_bonding.h | 72 #define BOND_MODE_ALB 6 /* TLB + RLB (receive load balancing) */
|
| /external/icu4c/tools/gencfu/ |
| gencfu.vcproj | 218 TypeLibraryName=".\x64\Release/gencfu.tlb"
309 TypeLibraryName=".\x64\Debug/gencfu.tlb"
|
| gencfu.vcxproj | 150 <TypeLibraryName>.\x64\Release/gencfu.tlb</TypeLibraryName>
187 <TypeLibraryName>.\x64\Debug/gencfu.tlb</TypeLibraryName>
|
| /external/oprofile/events/i386/p4/ |
| unit_masks | 114 0x01 page walk for data TLB miss
115 0x02 page walk for instruction TLB miss
|
| /external/oprofile/events/ppc64/ibm-compat-v1/ |
| events | 55 event:0X0063 counters:3 um:zero minimum:1000 name:PM_ITLB_MISS_GRP6 : (Group 6 pm_compat_instruction_directory) Instruction TLB misses
60 event:0X0072 counters:2 um:zero minimum:1000 name:PM_DTLB_MISS_GRP7 : (Group 7 pm_compat_data_directory) Data TLB misses
|
| /external/qemu/tcg/hppa/ |
| tcg-target.c | 892 /* Load and compare a TLB entry, and branch if TLB miss. OFFSET is set to
894 TLB for the memory index. The return value is the offset from ENV
903 /* Extracting the index into the TLB. The "normal C operation" is
935 /* Compute the value that ought to appear in the TLB for a hit, namely, the page
938 issued the load from the TLB slot to give the load time to complete. */
[all...] |
| /external/qemu/ |
| monitor.c | [all...] |
| cpu-all.h | 943 /* Flags stored in the low bits of the TLB virtual address. These are
945 /* Zero if TLB entry is valid. */
947 /* Set if TLB entry references a clean RAM page. The iotlb entry will
950 /* Set if TLB entry is an IO callback. */
|
| cpu-defs.h | 69 TLB invalidation to quickly clear a subset of the hash table. */
|
| /external/oprofile/events/ppc64/power5+/ |
| events | 189 event:0X160 counters:0 um:zero minimum:1000 name:PM_ITLB_MISS_GRP22 : (Group 22 pm_flush2) Instruction TLB misses
[all...] |
| /external/oprofile/events/mips/74K/ |
| events | 22 event:0x4 counters:0,2 um:zero minimum:500 name:ITLB_ACCESSES : 4-0 Instruction micro-TLB accesses
43 event:0x19 counters:0,2 um:zero minimum:500 name:JTLB_DATA_ACCESSES : 25-0 Joint TLB data (non-instruction) accesses
98 event:0x404 counters:1,3 um:zero minimum:500 name:ITLB_MISSES : 4-1 Instruction micro-TLB misses
99 event:0x405 counters:1,3 um:zero minimum:500 name:JTLB_INSN_MISSES : 5-1 Joint TLB instruction misses
119 event:0x419 counters:1,3 um:zero minimum:500 name:JTLB_DATA_MISSES : 25-1 Joint TLB data (non-instruction) misses
|
| /frameworks/compile/libbcc/tests/ |
| armreg.h | 191 * 8 TLB Control
195 * 10 TLB Lockdown
|
| /system/core/libpixelflinger/codeflinger/ |
| armreg.h | 191 * 8 TLB Control
195 * 10 TLB Lockdown
|
| /external/icu4c/layout/ |
| layout.vcproj | 48 TypeLibraryName=".\..\..\lib\iculed.tlb"
145 TypeLibraryName=".\..\..\lib\icule.tlb"
238 TypeLibraryName=".\..\..\lib64\iculed.tlb"
337 TypeLibraryName=".\..\..\lib64\icule.tlb"
|
| /external/icu4c/test/intltest/ |
| intltest.vcproj | 45 TypeLibraryName=".\x86\Debug/intltest.tlb"
138 TypeLibraryName=".\x64\Debug/intltest.tlb"
229 TypeLibraryName=".\x86\Release/intltest.tlb"
316 TypeLibraryName=".\x64\Release/intltest.tlb"
|
| intltest.vcxproj | 83 <TypeLibraryName>.\x86\Debug/intltest.tlb</TypeLibraryName>
123 <TypeLibraryName>.\x64\Debug/intltest.tlb</TypeLibraryName>
160 <TypeLibraryName>.\x86\Release/intltest.tlb</TypeLibraryName>
195 <TypeLibraryName>.\x64\Release/intltest.tlb</TypeLibraryName>
|
| /external/kernel-headers/original/asm-generic/ |
| pgtable.h | 9 * - inform the TLB about the new one
|
| /external/oprofile/events/mips/r10000/ |
| events | 20 event:0x07 counters:1 um:zero minimum:500 name:TLB_REFILL_EXCEPTIONS : TLB refill exceptions
|
| /external/oprofile/events/mips/r12000/ |
| events | 27 event:0x17 counters:0,1,2,3 um:zero minimum:500 name:TLB_MISSES : TLB misses
|
| /external/qemu/tcg/i386/ |
| tcg-target.c | 979 /* Perform the TLB load and compare.
992 positions of the displacements of forward jumps to the TLB miss case.
995 In the TLB hit case, it has been adjusted as indicated by the TLB
996 and so is a host address. In the TLB miss case, it continues to
1052 /* TLB Hit. */
[all...] |
