| /external/oprofile/events/mips/rm7000/ |
| events | 4 event:0x00 counters:0,1 um:zero minimum:500 name:CYCLES : Clock cycles
5 event:0x01 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS_ISSUED : Total instructions issued
6 event:0x02 counters:0,1 um:zero minimum:500 name:FP_INSTRUCTIONS_ISSUED : Floating-point instructions issued
7 event:0x03 counters:0,1 um:zero minimum:500 name:INTEGER_INSTRUCTIONS_ISSUED : Integer instructions issued
8 event:0x04 counters:0,1 um:zero minimum:500 name:LOAD_INSTRUCTIONS_ISSUED : Load instructions issued
9 event:0x05 counters:0,1 um:zero minimum:500 name:STORE_INSTRUCTIONS_ISSUED : Store instructions issued
10 event:0x06 counters:0,1 um:zero minimum:500 name:DUAL_ISSUED_PAIRS : Dual issued pairs
11 event:0x07 counters:0,1 um:zero minimum:500 name:BRANCH_PREFETCHES : Branch prefetches
12 event:0x08 counters:0,1 um:zero minimum:500 name:EXTERNAL_CACHE_MISSES : External Cache Misses
13 event:0x09 counters:0,1 um:zero minimum:500 name:STALL_CYCLES : Stall cycle
[all...] |
| /external/oprofile/events/mips/74K/ |
| events | 14 event:0x0 counters:0,1,2,3 um:zero minimum:500 name:CYCLES : 0-0 Cycles
15 event:0x1 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTIONS : 1-0 Instructions graduated
20 event:0x2 counters:0,2 um:zero minimum:500 name:PREDICTED_JR_31 : 2-0 JR $31 (return) instructions predicted including speculative instructions
21 event:0x3 counters:0,2 um:zero minimum:500 name:REDIRECT_STALLS : 3-0 Stall cycles due to register indirect jumps (including non-predicted JR $31), ERET/WAIT instructions, and IFU determined exception
22 event:0x4 counters:0,2 um:zero minimum:500 name:ITLB_ACCESSES : 4-0 Instruction micro-TLB accesses
24 event:0x6 counters:0,2 um:zero minimum:500 name:ICACHE_ACCESSES : 6-0 Instruction cache accesses including speculative instructions
25 event:0x7 counters:0,2 um:zero minimum:500 name:ICACHE_MISS_STALLS : 7-0 Instruction cache miss stall cycles
26 event:0x8 counters:0,2 um:zero minimum:500 name:UNCACHED_IFETCH_STALLS : 8-0 Uncached instruction fetch stall cycles
27 event:0x9 counters:0,2 um:zero minimum:500 name:IFU_REPLAYS : 9-0 Replays within the IFU due to full Instruction Buffer
29 event:0xb counters:0,2 um:zero minimum:500 name:IFU_IDU_MISS_PRED_UPSTREAM_CYCLES : 11-0 Cycles IFU-IDU gate is closed (to preven (…)
[all...] |
| /external/oprofile/events/i386/core/ |
| events | 6 event:0xc0 counters:0,1 um:zero minimum:6000 name:INST_RETIRED : number of instructions retired
11 event:0x03 counters:0,1 um:zero minimum:500 name:LD_BLOCKS : number of store buffer blocks
12 event:0x04 counters:0,1 um:zero minimum:500 name:SB_DRAINS : number of store buffer drain cycles
13 event:0x05 counters:0,1 um:zero minimum:500 name:MISALIGN_MEM_REF : number of misaligned data memory references
14 event:0x06 counters:0,1 um:zero minimum:500 name:SEGMENT_REG_LOADS : number of segment register loads
16 event:0x10 counters:0 um:zero minimum:3000 name:FLOPS : number of computational FP operations executed
17 event:0x11 counters:1 um:zero minimum:500 name:FP_ASSIST : number of FP exceptions handled by microcode
18 event:0x12 counters:1 um:zero minimum:1000 name:MUL : number of multiplies
19 event:0x13 counters:1 um:zero minimum:500 name:DIV : number of divides
20 event:0x14 counters:0 um:zero minimum:1000 name:CYCLES_DIV_BUSY : cycles divider is bus
[all...] |
| /external/oprofile/events/arm/armv7/ |
| events | 5 event:0x40 counters:1,2,3,4 um:zero minimum:500 name:WRITE_BUFFER_FULL : Any write buffer full cycle
6 event:0x41 counters:1,2,3,4 um:zero minimum:500 name:L2_STORE_MERGED : Any store that is merged in L2 cache
7 event:0x42 counters:1,2,3,4 um:zero minimum:500 name:L2_STORE_BUFF : Any bufferable store from load/store to L2 cache
8 event:0x43 counters:1,2,3,4 um:zero minimum:500 name:L2_ACCESS : Any access to L2 cache
9 event:0x44 counters:1,2,3,4 um:zero minimum:500 name:L2_CACH_MISS : Any cacheable miss in L2 cache
10 event:0x45 counters:1,2,3,4 um:zero minimum:500 name:AXI_READ_CYCLES : Number of cycles for an active AXI read
11 event:0x46 counters:1,2,3,4 um:zero minimum:500 name:AXI_WRITE_CYCLES : Number of cycles for an active AXI write
12 event:0x47 counters:1,2,3,4 um:zero minimum:500 name:MEMORY_REPLAY : Any replay event in the memory subsystem
13 event:0x48 counters:1,2,3,4 um:zero minimum:500 name:UNALIGNED_ACCESS_REPLAY : Unaligned access that causes a replay
14 event:0x49 counters:1,2,3,4 um:zero minimum:500 name:L1_DATA_MISS : L1 data cache miss as a result of the hashing algorith
[all...] |
| /external/oprofile/events/arm/armv7-common/ |
| events | 4 event:0x00 counters:1,2,3,4,5,6 um:zero minimum:500 name:PMNC_SW_INCR : Software increment of PMNC registers
5 event:0x01 counters:1,2,3,4,5,6 um:zero minimum:500 name:IFETCH_MISS : Instruction fetch misses from cache or normal cacheable memory
6 event:0x02 counters:1,2,3,4,5,6 um:zero minimum:500 name:ITLB_MISS : Instruction fetch misses from TLB
7 event:0x03 counters:1,2,3,4,5,6 um:zero minimum:500 name:DCACHE_REFILL : Data R/W operation that causes a refill from cache or normal cacheable memory
8 event:0x04 counters:1,2,3,4,5,6 um:zero minimum:500 name:DCACHE_ACCESS : Data R/W from cache
9 event:0x05 counters:1,2,3,4,5,6 um:zero minimum:500 name:DTLB_REFILL : Data R/W that causes a TLB refill
10 event:0x06 counters:1,2,3,4,5,6 um:zero minimum:500 name:DREAD : Data read architecturally executed (note: architecturally executed = for instructions that are unconditional or that pass the condition code)
11 event:0x07 counters:1,2,3,4,5,6 um:zero minimum:500 name:DWRITE : Data write architecturally executed
12 event:0x08 counters:1,2,3,4,5,6 um:zero minimum:500 name:INSTR_EXECUTED : All executed instructions
13 event:0x09 counters:1,2,3,4,5,6 um:zero minimum:500 name:EXC_TAKEN : Exception take
[all...] |
| /external/llvm/test/CodeGen/Generic/ |
| zero-sized-array.ll | 4 %zero = type [0 x i8]
5 %foobar = type { i32, %zero }
10 call i32 @f2(%zero %arg2, i32 5, i32 42)
14 define i32 @f2(%zero %x, i32 %y, i32 %z) {
18 define void @f3(%zero %x, i32 %y) {
19 call i32 @f2(%zero %x, i32 5, i32 %y)
23 define void @f4(%zero %z) {
24 insertvalue %foobar undef, %zero %z, 1
34 %insert120 = insertvalue %foobar undef, %zero %y, 1
38 define void @f6(%zero %x, %zero %y)
[all...] |
| /external/oprofile/events/arm/armv7-ca9/ |
| events | 5 event:0x40 counters:1,2,3,4,5,6 um:zero minimum:500 name:JAVA_BC_EXEC : Number of Java bytecodes decoded, including speculative ones
6 event:0x41 counters:1,2,3,4,5,6 um:zero minimum:500 name:JAVA_SFTBC_EXEC : Number of software Java bytecodes decoded, including speculative ones
7 event:0x42 counters:1,2,3,4,5,6 um:zero minimum:500 name:JAVA_BB_EXEC : Number of Jazelle taken branches executed, including those flushed due to a previous load/store which aborts late
9 event:0x50 counters:1,2,3,4,5,6 um:zero minimum:500 name:CO_LF_MISS : Number of coherent linefill requests which miss in all other CPUs, meaning that the request is sent to external memory
10 event:0x51 counters:1,2,3,4,5,6 um:zero minimum:500 name:CO_LF_HIT : Number of coherent linefill requests which hit in another CPU, meaning that the linefill data is fetched directly from the relevant cache
12 event:0x60 counters:1,2,3,4,5,6 um:zero minimum:500 name:IC_DEP_STALL : Number of cycles where CPU is ready to accept new instructions but does not receive any because of the instruction side not being able to provide any and the instruction cache is currently performing at least one linefill
13 event:0x61 counters:1,2,3,4,5,6 um:zero minimum:500 name:DC_DEP_STALL : Number of cycles where CPU has some instructions that it cannot issue to any pipeline and the LSU has at least one pending linefill request but no pending TLB requests
14 event:0x63 counters:1,2,3,4,5,6 um:zero minimum:500 name:STREX_PASS : Number of STREX instructions architecturally executed and passed
15 event:0x64 counters:1,2,3,4,5,6 um:zero minimum:500 name:STREX_FAILS : Number of STREX instructions architecturally executed and failed
16 event:0x65 counters:1,2,3,4,5,6 um:zero minimum:500 name:DATA_EVICT : Number of eviction requests due to a linefill in the data cach
[all...] |
| /external/oprofile/events/ppc/e300/ |
| events | 3 event:0x1 counters:0,1,2,3 um:zero minimum:3000 name:CPU_CLK : Cycles
4 event:0x2 counters:0,1,2,3 um:zero minimum:3000 name:COMPLETED_INSNS : Completed Instructions (0, 1, or 2 per cycle)
5 event:0x4 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_FETCHES : Instruction fetches
6 event:0x6 counters:0,1,2,3 um:zero minimum:500 name:PM_EVENT_TRANS : 0 to 1 translations on the pm_event input
7 event:0x7 counters:0,1,2,3 um:zero minimum:500 name:PM_EVENT_CYCLES : processor bus cycle
8 event:0x8 counters:0,1,2,3 um:zero minimum:500 name:COMPLETED_BRANCHES : Branch Instructions completed
9 event:0x9 counters:0,1,2,3 um:zero minimum:500 name:COMPLETED_LOAD_OPS : Load micro-ops completed
10 event:0xa counters:0,1,2,3 um:zero minimum:500 name:COMPLETED_STORE_OPS : Store micro-ops completed
11 event:0xc counters:0,1,2,3 um:zero minimum:500 name:BRANCHES_FINISHED : Branches finished
12 event:0xd counters:0,1,2,3 um:zero minimum:500 name:TAKEN_BRANCHES_FINISHED : Taken branches finishe
[all...] |
| /external/icu4c/common/ |
| ucnvisci.c | 33 #define ZWNJ 0x200c /* Zero Width Non Joiner */
34 #define ZWJ 0x200d /* Zero width Joiner */
116 ZERO =0x00
290 /*0xa0 : 0x00: 0x900 */ ZERO + ZERO + ZERO + ZERO + ZERO + ZERO + ZERO + ZERO
[all...] |
| /external/oprofile/events/i386/p6_mobile/ |
| events | 3 event:0x79 counters:0,1 um:zero minimum:6000 name:CPU_CLK_UNHALTED : clocks processor is not halted, and not in a thermal trip
4 event:0x43 counters:0,1 um:zero minimum:500 name:DATA_MEM_REFS : all memory references, cachable and non
5 event:0x45 counters:0,1 um:zero minimum:500 name:DCU_LINES_IN : total lines allocated in the DCU
6 event:0x46 counters:0,1 um:zero minimum:500 name:DCU_M_LINES_IN : number of M state lines allocated in DCU
7 event:0x47 counters:0,1 um:zero minimum:500 name:DCU_M_LINES_OUT : number of M lines evicted from the DCU
8 event:0x48 counters:0,1 um:zero minimum:500 name:DCU_MISS_OUTSTANDING : number of cycles while DCU miss outstanding
9 event:0x80 counters:0,1 um:zero minimum:500 name:IFU_IFETCH : number of non/cachable instruction fetches
10 event:0x81 counters:0,1 um:zero minimum:500 name:IFU_IFETCH_MISS : number of instruction fetch misses
11 event:0x85 counters:0,1 um:zero minimum:500 name:ITLB_MISS : number of ITLB misses
12 event:0x86 counters:0,1 um:zero minimum:500 name:IFU_MEM_STALL : cycles instruction fetch pipe is stalle
[all...] |
| /external/oprofile/events/mips/1004K/ |
| events | 14 event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : 0-0 Cycles
15 event:0x1 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS : 1-0 Instructions completed
16 event:0xb counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : 11-0 Data cache misses
21 event:0x2 counters:0 um:zero minimum:500 name:BRANCH_INSNS : 2-0 Branch instructions (whether completed or mispredicted)
22 event:0x3 counters:0 um:zero minimum:500 name:JR_31_INSNS : 3-0 JR $31 (return) instructions executed
23 event:0x4 counters:0 um:zero minimum:500 name:JR_NON_31_INSNS : 4-0 JR $xx (not $31) instructions executed (at same cost as a mispredict)
24 event:0x5 counters:0 um:zero minimum:500 name:ITLB_ACCESSES : 5-0 Instruction micro-TLB accesses
25 event:0x6 counters:0 um:zero minimum:500 name:DTLB_ACCESSES : 6-0 Data micro-TLB accesses
26 event:0x7 counters:0 um:zero minimum:500 name:JTLB_INSN_ACCESSES : 7-0 Joint TLB instruction accesses
27 event:0x8 counters:0 um:zero minimum:500 name:JTLB_DATA_ACCESSES : 8-0 Joint TLB data (non-instruction) accesse
[all...] |
| /external/oprofile/events/i386/ppro/ |
| events | 3 event:0x79 counters:0,1 um:zero minimum:6000 name:CPU_CLK_UNHALTED : clocks processor is not halted
4 event:0x43 counters:0,1 um:zero minimum:500 name:DATA_MEM_REFS : all memory references, cachable and non
5 event:0x45 counters:0,1 um:zero minimum:500 name:DCU_LINES_IN : total lines allocated in the DCU
6 event:0x46 counters:0,1 um:zero minimum:500 name:DCU_M_LINES_IN : number of M state lines allocated in DCU
7 event:0x47 counters:0,1 um:zero minimum:500 name:DCU_M_LINES_OUT : number of M lines evicted from the DCU
8 event:0x48 counters:0,1 um:zero minimum:500 name:DCU_MISS_OUTSTANDING : number of cycles while DCU miss outstanding
9 event:0x80 counters:0,1 um:zero minimum:500 name:IFU_IFETCH : number of non/cachable instruction fetches
10 event:0x81 counters:0,1 um:zero minimum:500 name:IFU_IFETCH_MISS : number of instruction fetch misses
11 event:0x85 counters:0,1 um:zero minimum:500 name:ITLB_MISS : number of ITLB misses
12 event:0x86 counters:0,1 um:zero minimum:500 name:IFU_MEM_STALL : cycles instruction fetch pipe is stalle
[all...] |
| /libcore/luni/src/test/java/libcore/java/lang/ |
| ByteTest.java | 22 final byte zero = (byte) 0;
26 assertTrue(Byte.compare(zero, zero) == 0);
27 assertTrue(Byte.compare(max, zero) > 0);
29 assertTrue(Byte.compare(zero, max) < 0);
30 assertTrue(Byte.compare(zero, min) > 0);
31 assertTrue(Byte.compare(min, zero) < 0);
|
| IntegerTest.java | 22 final int zero = 0; local
26 assertTrue(Integer.compare(zero, zero) == 0);
27 assertTrue(Integer.compare(max, zero) > 0);
29 assertTrue(Integer.compare(zero, max) < 0);
30 assertTrue(Integer.compare(zero, min) > 0);
31 assertTrue(Integer.compare(min, zero) < 0);
|
| LongTest.java | 22 final long zero = 0L; local
26 assertTrue(Long.compare(zero, zero) == 0);
27 assertTrue(Long.compare(max, zero) > 0);
29 assertTrue(Long.compare(zero, max) < 0);
30 assertTrue(Long.compare(zero, min) > 0);
31 assertTrue(Long.compare(min, zero) < 0);
|
| ShortTest.java | 22 final short zero = 0; local
26 assertTrue(Short.compare(zero, zero) == 0);
27 assertTrue(Short.compare(max, zero) > 0);
29 assertTrue(Short.compare(zero, max) < 0);
30 assertTrue(Short.compare(zero, min) > 0);
31 assertTrue(Short.compare(min, zero) < 0);
|
| /external/oprofile/events/ia64/itanium/ |
| events | 2 event:0x12 counters:0,1,2,3 um:zero minimum:500 name:CPU_CYCLES : CPU Cycles
3 event:0x08 counters:0,1 um:zero minimum:500 name:IA64_INST_RETIRED : IA-64 Instructions Retired
4 event:0x15 counters:0,1,2,3 um:zero minimum:500 name:IA32_INST_RETIRED : IA-32 Instructions Retired
|
| /bionic/libc/arch-x86/bionic/ |
| crtend_so.S | 12 .zero 4
|
| /external/clang/test/CodeGenCXX/ |
| debug-info-namespace.cpp | 6 ZERO,
|
| /external/dropbear/libtomcrypt/src/misc/ |
| zeromem.c | 15 Zero a block of memory, Tom St Denis
19 Zero a block of memory
20 @param out The destination of the area to zero
21 @param outlen The length of the area to zero (octets)
|
| /external/oprofile/events/mips/r12000/ |
| unit_masks | 6 name:zero type:mandatory default:0x0
|
| /external/oprofile/events/mips/34K/ |
| events | 14 event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : 0-0 Cycles
15 event:0x1 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS : 1-0 Instructions completed
16 event:0xb counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : 11-0 Data cache misses
21 event:0x2 counters:0 um:zero minimum:500 name:BRANCH_INSNS : 2-0 Branch instructions (whether completed or mispredicted)
22 event:0x3 counters:0 um:zero minimum:500 name:JR_31_INSNS : 3-0 JR $31 (return) instructions executed
23 event:0x4 counters:0 um:zero minimum:500 name:JR_NON_31_INSNS : 4-0 JR $xx (not $31) instructions executed (at same cost as a mispredict)
24 event:0x5 counters:0 um:zero minimum:500 name:ITLB_ACCESSES : 5-0 Instruction micro-TLB accesses
25 event:0x6 counters:0 um:zero minimum:500 name:DTLB_ACCESSES : 6-0 Data micro-TLB accesses
26 event:0x7 counters:0 um:zero minimum:500 name:JTLB_INSN_ACCESSES : 7-0 Joint TLB instruction accesses
27 event:0x8 counters:0 um:zero minimum:500 name:JTLB_DATA_ACCESSES : 8-0 Joint TLB data (non-instruction) accesse
[all...] |
| /external/llvm/test/CodeGen/X86/ |
| subreg-to-reg-0.ll | 3 ; Do eliminate the zero-extension instruction and rely on
4 ; x86-64's implicit zero-extension!
|
| /external/llvm/test/MC/ELF/ |
| org.s | 3 .zero 4
5 .zero 4
|
| /external/srec/doc/logs/srec/ |
| out_SHIP_change_sample_rate2.txt | 15 C: oh eight four zero nine two five one eight five
21 TRANSCRIPTION : 'oh eight four zero nine two five one eight five'
137 C: zero seven six five nine oh zero two five two
143 TRANSCRIPTION : 'zero seven six five nine oh zero two five two'
144 LITERAL[ 0] : 'zero seven six five nine oh zero two five two'
149 LITERAL[ 1] : 'zero seven seven five nine oh zero two five two
[all...] |
