| /external/valgrind/main/none/tests/ |
| fork.c | 13 /* Sometimes child goes first (non-zero), sometimes parent (zero). This
14 printing means we can detect if we correctly get a zero result and a
15 non-zero result (--> three 'X's printed), but the output doesn't depend
|
| /external/oprofile/events/alpha/ev67/ |
| events | 3 event:0x00 counters:0 um:zero minimum:500 name:CYCLES : Total cycles
4 event:0x01 counters:1 um:zero minimum:500 name:DELAYED_CYCLES : Cycles of delayed retire pointer advance
6 event:0x00 counters:0,1 um:zero minimum:500 name:RETIRED : Retired instructions
7 event:0x02 counters:1 um:zero minimum:500 name:BCACHE_MISS : Bcache misses/long probe latency
8 event:0x03 counters:1 um:zero minimum:500 name:MBOX_REPLAY : Mbox replay traps
10 event:0x04 counters:0 um:zero minimum:500 name:STALLED_0 : PCTR0 triggered; stalled between fetch and map stages
11 event:0x05 counters:0 um:zero minimum:500 name:TAKEN_0 : PCTR0 triggered; branch was not mispredicted and taken
12 event:0x06 counters:0 um:zero minimum:500 name:MISPREDICT_0 : PCTR0 triggered; branch was mispredicted
13 event:0x07 counters:0 um:zero minimum:500 name:ITB_MISS_0 : PCTR0 triggered; ITB miss
14 event:0x08 counters:0 um:zero minimum:500 name:DTB_MISS_0 : PCTR0 triggered; DTB mis
[all...] |
| /external/oprofile/events/arm/mpcore/ |
| events | 3 event:0x00 counters:0,1 um:zero minimum:500 name:IFU_IFETCH_MISS : number of instruction fetch misses
4 event:0x01 counters:0,1 um:zero minimum:500 name:CYCLES_IFU_MEM_STALL : cycles instruction fetch pipe is stalled
5 event:0x02 counters:0,1 um:zero minimum:500 name:CYCLES_DATA_STALL : cycles stall occurs for due to data dependency
6 event:0x03 counters:0,1 um:zero minimum:500 name:ITLB_MISS : number of ITLB misses
7 event:0x04 counters:0,1 um:zero minimum:500 name:DTLB_MISS : number of DTLB misses
8 event:0x05 counters:0,1 um:zero minimum:500 name:BR_INST_EXECUTED : branch instruction executed w/ or w/o program flow change
9 event:0x06 counters:0,1 um:zero minimum:500 name:BR_INST_NOT_PRED : branch not predicted
10 event:0x07 counters:0,1 um:zero minimum:500 name:BR_INST_MISPRED : branch mispredicted
11 event:0x08 counters:0,1 um:zero minimum:500 name:INSN_EXECUTED : instruction executed
12 event:0x09 counters:0,1 um:zero minimum:500 name:INSN_FOLD_EXECUTED : folded instruction execute
[all...] |
| /external/oprofile/events/mips/24K/ |
| events | 14 event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : 0-0 Cycles
15 event:0x1 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS : 1-0 Instructions completed
16 event:0xb counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : 11-0 Data cache misses
21 event:0x2 counters:0 um:zero minimum:500 name:BRANCH_INSNS : 2-0 Branch instructions (whether completed or mispredicted)
22 event:0x3 counters:0 um:zero minimum:500 name:JR_31_INSNS : 3-0 JR $31 (return) instructions executed
23 event:0x4 counters:0 um:zero minimum:500 name:JR_NON_31_INSNS : 4-0 JR $xx (not $31) instructions executed (at same cost as a mispredict)
24 event:0x5 counters:0 um:zero minimum:500 name:ITLB_ACCESSES : 5-0 Instruction micro-TLB accesses
25 event:0x6 counters:0 um:zero minimum:500 name:DTLB_ACCESSES : 6-0 Data micro-TLB accesses
26 event:0x7 counters:0 um:zero minimum:500 name:JTLB_INSN_ACCESSES : 7-0 Joint TLB instruction accesses
27 event:0x8 counters:0 um:zero minimum:500 name:JTLB_DATA_ACCESSES : 8-0 Joint TLB data (non-instruction) accesse
[all...] |
| /external/oprofile/events/alpha/ev4/ |
| events | 3 event:0x00 counters:0 um:zero minimum:4096 name:ISSUES : Total issues divided by 2
4 event:0x02 counters:0 um:zero minimum:4096 name:PIPELINE_DRY : Nothing issued, no valid I-stream data
5 event:0x04 counters:0 um:zero minimum:4096 name:LOAD_INSNS : All load instructions
6 event:0x06 counters:0 um:zero minimum:4096 name:PIPELINE_FROZEN : Nothing issued, resource conflict
7 event:0x08 counters:0 um:zero minimum:4096 name:BRANCH_INSNS : All branches (conditional, unconditional, jsr, hw_rei)
8 event:0x0a counters:0 um:zero minimum:4096 name:CYCLES : Total cycles
9 event:0x0b counters:0 um:zero minimum:4096 name:PAL_MODE : Cycles while in PALcode environment
10 event:0x0c counters:0 um:zero minimum:4096 name:NON_ISSUES : Total nonissues divided by 2
11 event:0x10 counters:0 um:zero minimum:256 name:DCACHE_MISSES : Total D-cache misses
12 event:0x11 counters:0 um:zero minimum:256 name:ICACHE_MISSES : Total I-cache misse
[all...] |
| /external/oprofile/events/mips/vr5432/ |
| events | 4 event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : Processor cycles (PClock)
5 event:0x1 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS_EXECUTED : (Instructions executed)/2 and truncated
6 event:0x2 counters:0,1 um:zero minimum:500 name:LOAD_PREF_CACHE_INSTRUCTIONS : Load, prefetch/CacheOps execution (no sync)
7 event:0x3 counters:0,1 um:zero minimum:500 name:STORES : Store execution
8 event:0x4 counters:0,1 um:zero minimum:500 name:BRANCHES : Branch execution (no jumps or jump registers)
9 event:0x5 counters:0,1 um:zero minimum:500 name:FP_INSTRUCTIONS : (FP instruction execution) / 2 and truncated excluding cp1 loads and stores
10 event:0x6 counters:0,1 um:zero minimum:500 name:DOUBLEWORDS_FLUSHED : Doublewords flushed to main memory (no uncached stores)
11 event:0x7 counters:0,1 um:zero minimum:500 name:JTLB_REFILLS : JTLB refills
12 event:0x8 counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : Data cache misses (no I-cache misses)
13 event:0x9 counters:0,1 um:zero minimum:500 name:ICACHE_MISSES : Instruction cache misses (no D-cache misses
[all...] |
| /external/oprofile/events/ppc64/pa6t/ |
| events | 9 event:0x1 counters:0 um:zero minimum:10000 name:CYCLES : Processor Cycles
10 event:0x3 counters:3 um:zero minimum:10000 name:ISS_CYCLES : Processor Cycles with instructions issued
11 event:0x4 counters:4 um:zero minimum:10000 name:RET_UOP : Retired Micro-operatioins
14 event:0x10 counters:0 um:zero minimum:10000 name:GRP1_CYCLES : Processor Cycles
15 event:0x11 counters:1 um:zero minimum:10000 name:GRP1_INST_RETIRED : Instructions retired
16 event:0x12 counters:2 um:zero minimum:1000 name:GRP1_DCACHE_RD_MISS__NS : Dcache read misses NS
17 event:0x13 counters:3 um:zero minimum:500 name:GRP1_MRB_LD_MISS_L2__NS : Load misses filling from memory
18 event:0x14 counters:4 um:zero minimum:500 name:GRP1_MRB_ST_MISS_ALLOC__NS : Store misses in L1D and allocates an MRB entry
19 event:0x15 counters:5 um:zero minimum:500 name:GRP1_TLB_MISS_D__NS : TLB misses NS (D- only)
22 event:0x20 counters:0 um:zero minimum:10000 name:GRP2_CYCLES : Processor Cycle
[all...] |
| /external/oprofile/events/arm/armv6/ |
| events | 3 event:0x00 counters:0,1 um:zero minimum:500 name:IFU_IFETCH_MISS : number of instruction fetch misses
4 event:0x01 counters:0,1 um:zero minimum:500 name:CYCLES_IFU_MEM_STALL : cycles instruction fetch pipe is stalled
5 event:0x02 counters:0,1 um:zero minimum:500 name:CYCLES_DATA_STALL : cycles stall occurs for due to data dependency
6 event:0x03 counters:0,1 um:zero minimum:500 name:ITLB_MISS : number of Instruction MicroTLB misses
7 event:0x04 counters:0,1 um:zero minimum:500 name:DTLB_MISS : number of Data MicroTLB misses
8 event:0x05 counters:0,1 um:zero minimum:500 name:BR_INST_EXECUTED : branch instruction executed w/ or w/o program flow change
9 event:0x06 counters:0,1 um:zero minimum:500 name:BR_INST_MISS_PRED : branch mispredicted
10 event:0x07 counters:0,1 um:zero minimum:500 name:INSN_EXECUTED : instructions executed
11 event:0x09 counters:0,1 um:zero minimum:500 name:DCACHE_ACCESS : data cache access, cacheable locations
12 event:0x0a counters:0,1 um:zero minimum:500 name:DCACHE_ACCESS_ALL : data cache access, all location
[all...] |
| /external/oprofile/events/arm/xscale1/ |
| events | 3 event:0x00 counters:1,2 um:zero minimum:500 name:IFU_IFETCH_MISS : number of instruction fetch misses
4 event:0x01 counters:1,2 um:zero minimum:500 name:CYCLES_IFU_MEM_STALL : cycles instruction fetch pipe is stalled
5 event:0x02 counters:1,2 um:zero minimum:500 name:CYCLES_DATA_STALL : cycles stall occurs for due to data dependency
6 event:0x03 counters:1,2 um:zero minimum:500 name:ITLB_MISS : number of ITLB misses
7 event:0x04 counters:1,2 um:zero minimum:500 name:DTLB_MISS : number of DTLB misses
8 event:0x05 counters:1,2 um:zero minimum:500 name:BR_INST_EXECUTED : branch instruction executed w/ or w/o program flow change
9 event:0x06 counters:1,2 um:zero minimum:500 name:BR_INST_MISS_PRED : branch mispredicted
10 event:0x07 counters:1,2 um:zero minimum:500 name:INSN_EXECUTED : instruction executed
11 event:0x08 counters:1,2 um:zero minimum:500 name:CYCLES_DCACHE_FULL_STALL : cycles in stall due to full dcache
12 event:0x09 counters:1,1 um:zero minimum:500 name:DCACHE_FULL_STALL_CNT : number of stalls due to dcache full conditio
[all...] |
| /external/oprofile/events/arm/xscale2/ |
| events | 3 event:0x00 counters:1,2,3,4 um:zero minimum:500 name:IFU_IFETCH_MISS : number of instruction fetch misses
4 event:0x01 counters:1,2,3,4 um:zero minimum:500 name:CYCLES_IFU_MEM_STALL : cycles instruction fetch pipe is stalled
5 event:0x02 counters:1,2,3,4 um:zero minimum:500 name:CYCLES_DATA_STALL : cycles stall occurs for due to data dependency
6 event:0x03 counters:1,2,3,4 um:zero minimum:500 name:ITLB_MISS : number of ITLB misses
7 event:0x04 counters:1,2,3,4 um:zero minimum:500 name:DTLB_MISS : number of DTLB misses
8 event:0x05 counters:1,2,3,4 um:zero minimum:500 name:BR_INST_EXECUTED : branch instruction executed w/ or w/o program flow change
9 event:0x06 counters:1,2,3,4 um:zero minimum:500 name:BR_INST_MISS_PRED : branch mispredicted
10 event:0x07 counters:1,2,3,4 um:zero minimum:500 name:INSN_EXECUTED : instruction executed
11 event:0x08 counters:1,2,3,4 um:zero minimum:500 name:CYCLES_DCACHE_FULL_STALL : cycles in stall due to full dcache
12 event:0x09 counters:1,2,3,4 um:zero minimum:500 name:DCACHE_FULL_STALL_CNT : number of stalls due to dcache full conditio
[all...] |
| /external/oprofile/events/i386/athlon/ |
| events | 3 event:0x76 counters:0,1,2,3 um:zero minimum:3000 name:CPU_CLK_UNHALTED : Cycles outside of halt state
4 event:0xc0 counters:0,1,2,3 um:zero minimum:3000 name:RETIRED_INSNS : Retired instructions (includes exceptions, interrupts, resyncs)
5 event:0xc1 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_OPS : Retired Ops
6 event:0x80 counters:0,1,2,3 um:zero minimum:500 name:ICACHE_FETCHES : Instruction cache fetches
7 event:0x81 counters:0,1,2,3 um:zero minimum:500 name:ICACHE_MISSES : Instruction cache misses
8 event:0x40 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_ACCESSES : Data cache accesses
9 event:0x41 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_MISSES : Data cache misses
13 event:0xc2 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_BRANCHES : Retired branches (conditional, unconditional, exceptions, interrupts)
14 event:0xc3 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_BRANCHES_MISPREDICTED : Retired branches mispredicted
15 event:0xc4 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_TAKEN_BRANCHES : Retired taken branche
[all...] |
| /external/oprofile/events/mips/5K/ |
| events | 8 event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : Cycles
9 event:0x2 counters:0,1 um:zero minimum:500 name:LOADS_EXECED : Load/pref(x)/sync/cache-ops executed
10 event:0x3 counters:0,1 um:zero minimum:500 name:STORES_EXECED : Stores (including conditional stores) executed
11 event:0x4 counters:0,1 um:zero minimum:500 name:COND_STORES_EXECED : Conditional stores executed
16 event:0x1 counters:0 um:zero minimum:500 name:INSN_FETCHED : Instructions fetched
17 event:0x5 counters:0 um:zero minimum:500 name:FAILED_COND_STORES : Failed conditional stores
18 event:0x6 counters:0 um:zero minimum:500 name:BRANCHES_EXECED : Branches executed
19 event:0x7 counters:0 um:zero minimum:500 name:ITLB_MISSES : ITLB miss
20 event:0x8 counters:0 um:zero minimum:500 name:DTLB_MISSES : DTLB miss
21 event:0x9 counters:0 um:zero minimum:500 name:ICACHE_MISS : Instruction cache mis
[all...] |
| /external/oprofile/events/ppc64/power5+/ |
| events | 14 event:0X001 counters:3 um:zero minimum:10000 name:CYCLES : Processor Cycles using continuous sampling
17 event:0X002 counters:2 um:zero minimum:10000 name:CYCLES_RND_SMPL : Processor Cycles with random sampling
21 event:0X010 counters:0 um:zero minimum:10000 name:PM_RUN_CYC_GRP1 : (Group 1 pm_utilization) Run cycles
22 event:0X011 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP1 : (Group 1 pm_utilization) Instructions completed
23 event:0X012 counters:2 um:zero minimum:1000 name:PM_INST_DISP_GRP1 : (Group 1 pm_utilization) Instructions dispatched
24 event:0X013 counters:3 um:zero minimum:10000 name:PM_CYC_GRP1 : (Group 1 pm_utilization) Processor cycles
25 event:0X014 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP1 : (Group 1 pm_utilization) Run instructions completed
26 event:0X015 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP1 : (Group 1 pm_utilization) Run cycles
29 event:0X020 counters:0 um:zero minimum:1000 name:PM_1PLUS_PPC_CMPL_GRP2 : (Group 2 pm_completion) One or more PPC instruction completed
30 event:0X021 counters:1 um:zero minimum:1000 name:PM_GCT_EMPTY_CYC_GRP2 : (Group 2 pm_completion) Cycles GCT empt
[all...] |
| /external/iptables/extensions/ |
| libxt_quota.man | 2 packet. The condition matches until the byte counter reaches zero. Behavior
4 byte counter reaches zero).
|
| /external/llvm/test/CodeGen/Mips/ |
| frame-address.ll | 10 ; CHECK: addu $fp, $sp, $zero
11 ; CHECK: addu $2, $zero, $fp
|
| /external/llvm/test/Transforms/ConstProp/ |
| div-zero.ll | 7 %zero = sub i32 %ptr, %ptr ; <i32> [#uses=1]
8 %div_zero = sdiv i32 %zero, ptrtoint (i32* getelementptr (i32* null,
|
| /external/oprofile/events/ia64/ia64/ |
| events | 2 event:0x12 counters:0,1,2,3 um:zero minimum:500 name:CPU_CYCLES : CPU Cycles
3 event:0x08 counters:0,1,2,3 um:zero minimum:500 name:IA64_INST_RETIRED : IA-64 Instructions Retired
|
| /external/valgrind/main/drd/tests/ |
| new_delete.cpp | 7 int zero = 0; local
13 q = new int[zero];
|
| /external/valgrind/main/massif/tests/ |
| zero.c | 1 // Test zero-size allocations -- shouldn't cause division by zero, that kind
|
| /external/oprofile/events/ppc/e500/ |
| events | 3 event:0x1 counters:0,1,2,3 um:zero minimum:3000 name:CPU_CLK : Cycles
4 event:0x2 counters:0,1,2,3 um:zero minimum:3000 name:COMPLETED_INSNS : Completed Instructions (0, 1, or 2 per cycle)
5 event:0x3 counters:0,1,2,3 um:zero minimum:500 name:COMPLETED_OPS : Completed Micro-ops (counts 2 for load/store w/update)
6 event:0x4 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_FETCHES : Instruction fetches
7 event:0x5 counters:0,1,2,3 um:zero minimum:500 name:DECODED_OPS : Micro-ops decoded
8 event:0x8 counters:0,1,2,3 um:zero minimum:500 name:COMPLETED_BRANCHES : Branch Instructions completed
9 event:0x9 counters:0,1,2,3 um:zero minimum:500 name:COMPLETED_LOAD_OPS : Load micro-ops completed
10 event:0xa counters:0,1,2,3 um:zero minimum:500 name:COMPLETED_STORE_OPS : Store micro-ops completed
11 event:0xb counters:0,1,2,3 um:zero minimum:500 name:COMPLETION_REDIRECTS : Number of completion buffer redirects
12 event:0xc counters:0,1,2,3 um:zero minimum:500 name:BRANCHES_FINISHED : Branches finishe
[all...] |
| /external/oprofile/events/ppc/e500v2/ |
| events | 3 event:0x1 counters:0,1,2,3 um:zero minimum:100 name:CPU_CLK : Cycles
4 event:0x2 counters:0,1,2,3 um:zero minimum:500 name:COMPLETED_INSNS : Completed Instructions (0, 1, or 2 per cycle)
5 event:0x3 counters:0,1,2,3 um:zero minimum:500 name:COMPLETED_OPS : Completed Micro-ops (counts 2 for load/store w/update)
6 event:0x4 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_FETCHES : Instruction fetches
7 event:0x5 counters:0,1,2,3 um:zero minimum:500 name:DECODED_OPS : Micro-ops decoded
8 event:0x8 counters:0,1,2,3 um:zero minimum:500 name:COMPLETED_BRANCHES : Branch Instructions completed
9 event:0x9 counters:0,1,2,3 um:zero minimum:500 name:COMPLETED_LOAD_OPS : Load micro-ops completed
10 event:0xa counters:0,1,2,3 um:zero minimum:500 name:COMPLETED_STORE_OPS : Store micro-ops completed
11 event:0xb counters:0,1,2,3 um:zero minimum:500 name:COMPLETION_REDIRECTS : Number of completion buffer redirects
12 event:0xc counters:0,1,2,3 um:zero minimum:500 name:BRANCHES_FINISHED : Branches finishe
[all...] |
| /external/oprofile/events/ppc64/power4/ |
| events | 14 event:0X001 counters:1 um:zero minimum:10000 name:CYCLES : Processor Cycles
18 event:0X010 counters:0 um:zero minimum:10000 name:PM_RUN_CYC_GRP1 : (Group 1 pm_slice0) Run cycles
19 event:0X011 counters:1 um:zero minimum:10000 name:PM_CYC_GRP1 : (Group 1 pm_slice0) Processor cycles
20 event:0X012 counters:2 um:zero minimum:1000 name:PM_STOP_COMPLETION_GRP1 : (Group 1 pm_slice0) Completion stopped
21 event:0X013 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP1 : (Group 1 pm_slice0) Instructions completed
22 event:0X014 counters:4 um:zero minimum:1000 name:PM_1PLUS_PPC_CMPL_GRP1 : (Group 1 pm_slice0) One or more PPC instruction completed
23 event:0X015 counters:5 um:zero minimum:10000 name:PM_CYC_GRP1 : (Group 1 pm_slice0) Processor cycles
24 event:0X016 counters:6 um:zero minimum:1000 name:PM_GRP_CMPL_GRP1 : (Group 1 pm_slice0) Group completed
25 event:0X017 counters:7 um:zero minimum:1000 name:PM_GRP_DISP_REJECT_GRP1 : (Group 1 pm_slice0) Group dispatch rejected
28 event:0X020 counters:0 um:zero minimum:10000 name:PM_CYC_GRP2 : (Group 2 pm_eprof) Processor cycle
[all...] |
| /external/oprofile/events/ppc64/power5/ |
| events | 14 event:0X001 counters:3 um:zero minimum:10000 name:CYCLES : Processor Cycles using continuous sampling
17 event:0X002 counters:2 um:zero minimum:10000 name:CYCLES_RND_SMPL : Processor Cycles with random sampling
21 event:0X010 counters:0 um:zero minimum:10000 name:PM_RUN_CYC_GRP1 : (Group 1 pm_utilization) Run cycles
22 event:0X011 counters:1 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP1 : (Group 1 pm_utilization) IOPS instructions completed
23 event:0X012 counters:2 um:zero minimum:1000 name:PM_INST_DISP_GRP1 : (Group 1 pm_utilization) Instructions dispatched
24 event:0X013 counters:3 um:zero minimum:10000 name:PM_CYC_GRP1 : (Group 1 pm_utilization) Processor cycles
25 event:0X014 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP1 : (Group 1 pm_utilization) Instructions completed
26 event:0X015 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP1 : (Group 1 pm_utilization) Run cycles
29 event:0X020 counters:0 um:zero minimum:1000 name:PM_1PLUS_PPC_CMPL_GRP2 : (Group 2 pm_completion) One or more PPC instruction completed
30 event:0X021 counters:1 um:zero minimum:1000 name:PM_GCT_EMPTY_CYC_GRP2 : (Group 2 pm_completion) Cycles GCT empt
[all...] |
| /external/oprofile/events/mips/r10000/ |
| events | 6 event:0x00 counters:0,1 um:zero minimum:500 name:CYCLES : Cycles
7 event:0x01 counters:0 um:zero minimum:500 name:INSTRUCTIONS_ISSUED : Instructions issued
8 event:0x01 counters:1 um:zero minimum:500 name:INSTRUCTIONS_GRADUATED : Instructions graduated
9 event:0x02 counters:0 um:zero minimum:500 name:LOAD_PREFETC_SYNC_CACHEOP_ISSUED : Load / prefetch / sync / CacheOp issued
10 event:0x02 counters:1 um:zero minimum:500 name:LOAD_PREFETC_SYNC_CACHEOP_GRADUATED : Load / prefetch / sync / CacheOp graduated
11 event:0x03 counters:0 um:zero minimum:500 name:STORES_ISSUED : Stores issued
12 event:0x03 counters:1 um:zero minimum:500 name:STORES_GRADUATED : Stores graduated
13 event:0x04 counters:0 um:zero minimum:500 name:STORE_COND_ISSUED : Store conditional issued
14 event:0x04 counters:1 um:zero minimum:500 name:STORE_COND_GRADUATED : Store conditional graduated
15 event:0x05 counters:0 um:zero minimum:500 name:FAILED_STORE_CONDITIONAL : Failed store conditiona
[all...] |
| /external/oprofile/events/mips/r12000/ |
| events | 4 event:0x0 counters:0,1,2,3 um:zero minimum:500 name:CYCLES : Cycles
5 event:0x1 counters:0,1,2,3 um:zero minimum:500 name:DECODED_INSTRUCTIONS : Decoded instructions
6 event:0x2 counters:0,1,2,3 um:zero minimum:500 name:DECODED_LOADS : Decoded loads
7 event:0x3 counters:0,1,2,3 um:zero minimum:500 name:DECODED_STORES : Decoded stores
8 event:0x4 counters:0,1,2,3 um:zero minimum:500 name:MISS_TABLE_OCCUPANCY : Miss Handling Table Occupancy
9 event:0x5 counters:0,1,2,3 um:zero minimum:500 name:FAILED_STORE_CONDITIONAL : Failed store conditional
10 event:0x6 counters:0,1,2,3 um:zero minimum:500 name:RESOLVED_BRANCH_CONDITIONAL : Resolved conditional branches
11 event:0x7 counters:0,1,2,3 um:zero minimum:500 name:QUADWORRDS_WRITEBACK_FROM_SC : Quadwords written back from secondary cache
12 event:0x8 counters:0,1,2,3 um:zero minimum:500 name:CORRECTABLE_ECC_ERRORS : Correctable ECC errors on secondary cache data
13 event:0x9 counters:0,1,2,3 um:zero minimum:500 name:ICACHE_MISSES : Instruction cache misse
[all...] |
