| /external/llvm/utils/TableGen/ |
| DAGISelMatcher.h | 819 /// Reg - The def for the register that we're emitting. If this is null, then
821 const CodeGenRegister *Reg;
824 EmitRegisterMatcher(const CodeGenRegister *reg, MVT::SimpleValueType vt)
825 : Matcher(EmitRegister), Reg(reg), VT(vt) {}
827 const CodeGenRegister *getReg() const { return Reg; }
837 return cast<EmitRegisterMatcher>(M)->Reg == Reg &&
841 return ((unsigned)(intptr_t)Reg) << 4 | VT;
[all...] |
| DAGISelMatcherEmitter.cpp | 438 const CodeGenRegister *Reg = Matcher->getReg();
441 if (Reg && Reg->EnumValue > 255) {
443 OS << "TARGET_VAL(" << getQualifiedName(Reg->TheDef) << "),\n";
447 if (Reg) {
448 OS << getQualifiedName(Reg->TheDef) << ",\n";
|
| AsmMatcherEmitter.cpp | 360 static ResOperand getRegOp(Record *Reg) {
363 X.Register = Reg;
663 if (Record *Reg = getSingletonRegisterForAsmOperand(i, Info))
664 SingletonRegisters.insert(Reg);
813 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(RegName))
814 return Reg->TheDef;
[all...] |
| DAGISelMatcher.cpp | 218 if (Reg)
219 OS << Reg->getName();
|
| CodeGenTarget.cpp | 185 const CodeGenRegister *Reg = getRegBank().getReg(R);
190 if (RC.contains(Reg)) {
|
| /external/llvm/lib/Target/ARM/ |
| ARMAsmPrinter.cpp | 237 unsigned Reg = MLoc.getReg();
238 if (Reg >= ARM::S0 && Reg <= ARM::S31) {
244 unsigned SReg = Reg - ARM::S0;
265 } else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
271 unsigned QReg = Reg - ARM::Q0;
322 unsigned Reg = MO.getReg();
323 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
325 O << ARMInstPrinter::getRegisterName(Reg);
[all...] |
| ARMFastISel.cpp | 69 unsigned Reg;
78 Base.Reg = 0;
497 // the combined constant into an FP reg.
534 // The extra reg is for addrmode5.
816 // Materialize the global variable's address into a reg which can
822 Addr.Base.Reg = Tmp;
827 if (Addr.Base.Reg == 0) Addr.Base.Reg = getRegForValue(Obj);
828 return Addr.Base.Reg != 0;
[all...] |
| ARMBaseInstrInfo.cpp | 239 unsigned Reg = MO.getReg();
241 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
243 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
245 LV->addVirtualRegisterDead(Reg, NewMI);
251 if (!NewMI->readsRegister(Reg))
253 LV->addVirtualRegisterKilled(Reg, NewMI);
686 llvm_unreachable("Impossible reg-to-reg copy");
691 unsigned Reg, unsigned SubIdx, unsigned State,
694 return MIB.addReg(Reg, State)
[all...] |
| ARMBaseInstrInfo.h | 199 /// FoldImmediate - 'Reg' is known to be defined by a move immediate
202 unsigned Reg, MachineRegisterInfo *MRI) const;
|
| Thumb1RegisterInfo.cpp | 552 unsigned Reg) const {
561 .addReg(Reg, RegState::Kill));
585 addReg(Reg, RegState::Define).addReg(ARM::R12, RegState::Kill));
673 // Use [reg, reg] addrmode. Replace the immediate operand w/ the frame
694 // Use [reg, reg] addrmode. Replace the immediate operand w/ the frame
|
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| AsmPrinter.cpp | 796 int Reg = TRI->getDwarfRegNum(MLoc.getReg(), false);
799 *SR && Reg < 0; ++SR) {
800 Reg = TRI->getDwarfRegNum(*SR, false);
810 // probably assert that Reg >= 0 once debug info generation is more mature.
813 if (Reg < 32) {
815 dwarf::OperationEncodingString(dwarf::DW_OP_breg0 + Reg));
816 EmitInt8(dwarf::DW_OP_breg0 + Reg);
820 OutStreamer.AddComment(Twine(Reg));
821 EmitULEB128(Reg);
825 if (Reg < 32)
[all...] |
| /external/llvm/lib/Target/Blackfin/ |
| BlackfinISelLowering.cpp | 191 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
192 MF.getRegInfo().addLiveIn(VA.getLocReg(), Reg);
193 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
350 // Build a sequence of copy-to-reg nodes chained together with token
391 unsigned Reg = RV.getLocReg();
393 Chain = DAG.getCopyFromReg(Chain, dl, Reg,
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGBuilder.cpp | 581 unsigned Reg, Type *Ty) {
589 Regs.push_back(Reg + i);
591 Reg += NumRegs;
[all...] |
| FunctionLoweringInfo.cpp | 243 FunctionLoweringInfo::GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth) {
244 if (!LiveOutRegInfo.inBounds(Reg))
247 LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
|
| SelectionDAGISel.cpp | 307 unsigned Reg = MI->getOperand(0).getReg();
308 if (TargetRegisterInfo::isPhysicalRegister(Reg))
311 MachineInstr *Def = RegInfo->getVRegDef(Reg);
317 // If Reg is live-in then update debug info to track its copy in a vreg.
318 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
702 unsigned Reg = TLI.getExceptionAddressRegister();
703 if (Reg) MBB->addLiveIn(Reg);
706 Reg = TLI.getExceptionSelectorRegister();
707 if (Reg) MBB->addLiveIn(Reg)
[all...] |
| /external/valgrind/main/VEX/priv/ |
| host_ppc_defs.c | 47 void ppHRegPPC ( HReg reg )
60 if (hregIsVirtual(reg)) {
61 ppHReg(reg);
65 switch (hregClass(reg)) {
67 r = hregNumber(reg);
72 r = hregNumber(reg);
77 r = hregNumber(reg);
82 r = hregNumber(reg);
204 // GPR0 = scratch reg where poss. - some ops interpret as value zero
240 // GPR30 is reserved as AltiVec spill reg temporar
3441 UInt reg = iregNo(i->Pin.RdWrLR.gpr, mode64); local
[all...] |
| host_amd64_defs.h | 129 Aam_IR, /* Immediate + Reg */
140 HReg reg; member in struct:__anon11862::__anon11863::__anon11864
160 /* --------- Operand, which can be reg, immediate or memory. --------- */
178 HReg reg; member in struct:__anon11867::__anon11868::__anon11870
179 } Reg;
195 /* --------- Operand, which can be reg or immediate only. --------- */
212 HReg reg; member in struct:__anon11873::__anon11874::__anon11876
213 } Reg;
225 /* --------- Operand, which can be reg or memory only. --------- */
239 HReg reg; member in struct:__anon11878::__anon11879::__anon11880
624 HReg reg; member in struct:__anon11888::__anon11889::__anon11921
629 HReg reg; member in struct:__anon11888::__anon11889::__anon11922
[all...] |
| host_ppc_defs.h | 51 extern HReg hregPPC_GPR0 ( Bool mode64 ); // scratch reg / zero reg
199 Pam_IR=1, /* Immediate (signed 16-bit) + Reg */
228 /* --------- Operand, which can be a reg or a u16/s16. --------- */
246 HReg reg; member in struct:__anon12037::__anon12038::__anon12040
247 } Reg;
259 /* --------- Operand, which can be a reg or a u32/64. --------- */
273 HReg Reg;
285 /* --------- Operand, which can be a vector reg or a s6. --------- */
299 HReg Reg;
653 HReg reg; member in struct:__anon12054::__anon12055::__anon12077
701 HReg reg; member in struct:__anon12054::__anon12055::__anon12085
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| LiveInterval.h | 209 const unsigned reg; // the register or stack slot of this interval.
225 LiveInterval(unsigned Reg, float Weight)
226 : reg(Reg), weight(Weight) {}
529 (thisIndex == otherIndex && reg < other.reg));
|
| FastISel.h | 326 void UpdateValueMap(const Value* I, unsigned Reg, unsigned NumRegs = 1);
|
| /external/llvm/lib/CodeGen/ |
| ShrinkWrapping.cpp | 196 /// calcAnticInOut - calculate the anticipated in/out reg sets
234 /// calcAvailInOut - calculate the available in/out reg sets
412 unsigned Reg = CSI[inx].getReg();
413 // If instruction I reads or modifies Reg, add it to UsedCSRegs,
423 if (MOReg == Reg ||
425 TargetRegisterInfo::isPhysicalRegister(Reg) &&
426 TRI->isSubRegister(Reg, MOReg))) {
427 // CSR Reg is defined/used in block MBB.
672 /// of changes to spilled reg sets. Add MBB to the set of blocks
734 /// of changes to restored reg sets. Add MBB to the set of block
1068 unsigned reg = CSI[*I].getReg(); local
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.h | 287 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
|
| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 203 unsigned Reg = Op.getReg();
204 O << getRegisterName(Reg);
237 // REG 0 0 - e.g. R5
238 // REG REG 0,SH_OPC - e.g. R5, ROR R3
239 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
818 // REG 0 0 - e.g. R5
819 // REG IMM, SH_OPC - e.g. R5, LSL #3
825 unsigned Reg = MO1.getReg();
826 O << getRegisterName(Reg);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 53 // Make sure we re-emit a set of the global base reg if necessary
142 /// register can be improved, but it is wrong to substitute Reg+Reg for
143 /// Reg in an asm, because the load or store opcode would have to change.
176 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
177 if (RegInfo->getRegClass(Reg) == &PPC::VRRCRegClass) {
[all...] |
