| /external/llvm/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | 67 std::vector<SDNode*> WorkList;
76 void AddUsersToWorkList(SDNode *N) {
77 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
84 SDValue visit(SDNode *N);
89 void AddToWorkList(SDNode *N) {
96 void removeFromWorkList(SDNode *N) {
101 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
104 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
108 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
129 bool CombineToPreIndexedLoadStore(SDNode *N)
[all...] |
| SelectionDAG.cpp | 111 bool ISD::isBuildVectorAllOnes(const SDNode *N) {
152 bool ISD::isBuildVectorAllZeros(const SDNode *N) {
192 bool ISD::isScalarToVector(const SDNode *N) {
311 // SDNode Profile Support
354 /// AddNodeIDCustom - If this is an SDNode with special info, add this info to
356 static void AddNodeIDCustom(FoldingSetNodeID &ID, const SDNode *N) {
461 static void AddNodeIDNode(FoldingSetNodeID &ID, const SDNode *N) {
468 // Handle SDNode leafs with special info.
494 static bool doNotCSE(SDNode *N) {
520 SmallVector<SDNode*, 128> DeadNodes
[all...] |
| LegalizeIntegerTypes.cpp | 36 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
146 SDValue DAGTypeLegalizer::PromoteIntRes_MERGE_VALUES(SDNode *N,
152 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
159 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
205 SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) {
263 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
274 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
283 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
297 SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) {
309 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N)
[all...] |
| LegalizeTypes.cpp | 73 SmallVector<SDNode*, 16> NewNodes;
88 for (SDNode::use_iterator UI = I->use_begin(), UE = I->use_end();
169 SDNode *N = NewNodes[i];
170 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
212 SDNode *N = Worklist.back();
325 SDNode *M = AnalyzeNewNode(N);
355 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
357 SDNode *User = *UI;
453 SDNode *DAGTypeLegalizer::AnalyzeNewNode(SDNode *N)
[all...] |
| InstrEmitter.cpp | 42 unsigned InstrEmitter::CountResults(SDNode *Node) {
55 unsigned InstrEmitter::CountOperands(SDNode *Node) {
67 EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
92 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
94 SDNode *User = *UI;
171 unsigned InstrEmitter::getDstOfOnlyCopyToRegUse(SDNode *Node,
176 SDNode *User = *Node->use_begin();
187 void InstrEmitter::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
209 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
211 SDNode *User = *UI
[all...] |
| LegalizeVectorTypes.cpp | 34 void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
125 SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
132 SDValue DAGTypeLegalizer::ScalarizeVecRes_MERGE_VALUES(SDNode *N,
138 SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) {
144 SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) {
155 SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
161 SDValue DAGTypeLegalizer::ScalarizeVecRes_FP_ROUND(SDNode *N) {
168 SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
174 SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
205 SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N)
[all...] |
| LegalizeTypesGeneric.cpp | 34 void DAGTypeLegalizer::ExpandRes_MERGE_VALUES(SDNode *N, unsigned ResNo,
40 void DAGTypeLegalizer::ExpandRes_BITCAST(SDNode *N, SDValue &Lo, SDValue &Hi) {
150 void DAGTypeLegalizer::ExpandRes_BUILD_PAIR(SDNode *N, SDValue &Lo,
157 void DAGTypeLegalizer::ExpandRes_EXTRACT_ELEMENT(SDNode *N, SDValue &Lo,
169 void DAGTypeLegalizer::ExpandRes_EXTRACT_VECTOR_ELT(SDNode *N, SDValue &Lo,
203 void DAGTypeLegalizer::ExpandRes_NormalLoad(SDNode *N, SDValue &Lo,
244 void DAGTypeLegalizer::ExpandRes_VAARG(SDNode *N, SDValue &Lo, SDValue &Hi) {
269 SDValue DAGTypeLegalizer::ExpandOp_BITCAST(SDNode *N) {
298 SDValue DAGTypeLegalizer::ExpandOp_BUILD_VECTOR(SDNode *N) {
332 SDValue DAGTypeLegalizer::ExpandOp_EXTRACT_ELEMENT(SDNode *N)
[all...] |
| ScheduleDAGFast.cpp | 211 SDNode *N = SU->getNode();
232 SmallVector<SDNode*, 2> NewNodes;
240 SDNode *LoadNode = NewNodes[0];
384 SUnit *CopyFromSU = NewSUnit(static_cast<SDNode *>(NULL));
388 SUnit *CopyToSU = NewSUnit(static_cast<SDNode *>(NULL));
423 static EVT getPhysicalRegisterVT(SDNode *N, unsigned Reg,
479 for (SDNode *Node = SU->getNode(); Node; Node = Node->getGluedNode()) {
|
| LegalizeDAG.cpp | 110 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
111 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
116 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
121 SDNode *Node, bool isSigned);
122 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
125 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
131 void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
134 SDValue ExpandBUILD_VECTOR(SDNode *Node);
135 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.h | 290 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
291 SmallVectorImpl<SDNode*> &NewNodes) const;
308 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
319 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
|
| X86ISelLowering.h | 443 bool isVEXTRACTF128Index(SDNode *N);
448 bool isVINSERTF128Index(SDNode *N);
453 unsigned getShuffleSHUFImmediate(SDNode *N);
457 unsigned getShufflePSHUFHWImmediate(SDNode *N);
461 unsigned getShufflePSHUFLWImmediate(SDNode *N);
465 unsigned getShufflePALIGNRImmediate(SDNode *N);
470 unsigned getExtractVEXTRACTF128Immediate(SDNode *N);
475 unsigned getInsertVINSERTF128Immediate(SDNode *N);
556 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
560 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const
[all...] |
| X86ISelDAGToDAG.cpp | 171 virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
175 inline bool immSext8(SDNode *N) const {
181 inline bool i64immSExt32(SDNode *N) const {
190 SDNode *Select(SDNode *N);
191 SDNode *SelectAtomic64(SDNode *Node, unsigned Opc);
192 SDNode *SelectAtomicLoadAdd(SDNode *Node, EVT NVT)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.h | 151 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
162 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
213 SDNode *DefNode, unsigned DefIdx,
214 SDNode *UseNode, unsigned UseIdx) const;
248 SDNode *Node) const;
|
| ARMISelLowering.h | 247 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
260 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
262 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
263 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
292 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
300 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
351 Sched::Preference getSchedulingPreference(SDNode *N) const;
484 virtual bool isUsedByReturnOnly(SDNode *N) const;
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelDAGToDAG.cpp | 136 SDNode *Select(SDNode *Node);
138 bool TryFoldLoad(SDNode *P, SDValue N,
374 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
423 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
466 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
515 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
579 bool SystemZDAGToDAGISel::TryFoldLoad(SDNode *P, SDValue N,
587 SDNode *SystemZDAGToDAGISel::Select(SDNode *Node)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 87 static bool isRotateAndMask(SDNode *N, unsigned Mask, bool isShiftMask,
92 SDNode *getGlobalBaseReg();
96 SDNode *Select(SDNode *N);
98 SDNode *SelectBitfieldInsert(SDNode *N);
161 SDNode *SelectSETCC(SDNode *N);
233 SDNode *PPCDAGToDAGISel::getGlobalBaseReg() {
259 static bool isIntS16Immediate(SDNode *N, short &Imm)
[all...] |
| PPCISelLowering.h | 214 int isVSLDOIShuffleMask(SDNode *N, bool isUnary);
223 bool isAllNegativeZeroVector(SDNode *N);
227 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize);
233 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
254 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
290 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
293 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
|
| /external/llvm/lib/Target/ |
| TargetInstrInfo.cpp | 78 SDNode *DefNode, unsigned DefIdx,
79 SDNode *UseNode, unsigned UseIdx) const {
103 SDNode *N) const {
|
| /external/llvm/lib/Target/Alpha/ |
| AlphaISelLowering.h | 78 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
114 void LowerVAARG(SDNode *N, SDValue &Chain, SDValue &DataPtr,
|
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.h | 92 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
157 SDValue TryExpandADDWithMul(SDNode *Op, SelectionDAG &DAG) const;
158 SDValue ExpandADDSUB(SDNode *Op, SelectionDAG &DAG) const;
160 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
|
| /external/llvm/include/llvm/Target/ |
| TargetLowering.h | 54 class SDNode;
196 virtual Sched::Preference getSchedulingPreference(SDNode *N) const {
748 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
758 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ScheduleDAG.h | 35 class SDNode;
230 SDNode *Node; // Representative node.
278 /// an SDNode and any nodes flagged to it.
279 SUnit(SDNode *node, unsigned nodenum)
318 /// setNode - Assign the representative SDNode for this SUnit.
320 void setNode(SDNode *N) {
321 assert(!Instr && "Setting SDNode of SUnit with MachineInstr!");
325 /// getNode - Return the representative SDNode for this SUnit.
327 SDNode *getNode() const {
328 assert(!Instr && "Reading SDNode of SUnit with MachineInstr!")
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 170 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
|
| /external/llvm/lib/Target/Blackfin/ |
| BlackfinISelLowering.h | 38 virtual void ReplaceNodeResults(SDNode *N,
|
| /external/llvm/lib/Target/CellSPU/ |
| SPUHazardRecognizers.cpp | 52 const SDNode *Node = SU->getNode()->getFlaggedMachineNode();
|
