| /external/valgrind/main/VEX/priv/ |
| guest_arm_toIR.c | 10851 UInt opc = (INSN(22,21) << 2) | INSN(6,5); local
10899 UInt opc = (INSN(22,21) << 2) | INSN(6,5); local
11076 UInt opc = (bP << 3) | (bQ << 2) | (bR << 1) | bS; local
11541 UInt opc = (bP << 3) | (bQ << 2) | (bR << 1) | bS; local
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 424 unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem : local
428 SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue,
640 unsigned opc = N->getOpcode(); local
642 switch (opc) {
716 bool isFPCmp, unsigned Opc) {
755 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
757 BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg())
[all...] |
| /external/llvm/lib/VMCore/ |
| Core.cpp | 665 #define HANDLE_INST(num, opc, clas) case num: return LLVM##opc;
676 #define HANDLE_INST(num, opc, clas) case LLVM##opc: return num;
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetLowering.h | 321 unsigned opc; // target opcode member in struct:llvm::TargetLowering::IntrinsicInfo
[all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | 1489 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub; local
[all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | 3116 unsigned opc = fieldFromInstruction32(Insn, 4, 28); local
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGBuilder.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | [all...] |
