| /external/llvm/lib/Target/Sparc/ |
| SparcRegisterInfo.cpp | 32 const TargetInstrInfo &tii)
33 : SparcGenRegisterInfo(SP::I7), Subtarget(st), TII(tii) {
68 BuildMI(MBB, I, dl, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size);
102 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
104 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
|
| /external/llvm/lib/CodeGen/ |
| Splitter.h | 58 const TargetInstrInfo *tii; member in class:llvm::LoopSplitter
|
| BranchFolding.h | 29 const TargetInstrInfo *tii,
90 const TargetInstrInfo *TII;
|
| LiveRangeEdit.h | 67 /// tii.isTriviallyReMaterializable().
76 const TargetInstrInfo &tii,
|
| Splitter.cpp | 138 ls.tii->get(TargetOpcode::COPY))
172 ls.tii->get(TargetOpcode::COPY))
279 tii = mf->getTarget().getInstrInfo();
349 if (tii->AnalyzeBranch(*mbb, a, b, c)) {
421 if (!!tii->AnalyzeBranch(*predBlock, a, b, c)) {
432 return (!tii->AnalyzeBranch(*headerLayoutPred, a, b, c));
555 return (!tii->AnalyzeBranch(*outBlockLayoutPred, a, b, c) &&
556 !tii->AnalyzeBranch(*edge.first, a, b, c));
|
| BranchFolding.cpp | 145 if (!TII->isUnpredicatedTerminator(I))
172 const TargetInstrInfo *tii,
175 if (!tii) return false;
179 TII = tii;
190 if (!TII->AnalyzeBranch(*MBB, TBB, FBB, Cond, true))
389 TII->ReplaceTailWithBranchTo(OldInst, NewDest);
402 if (!TII->isLegalToSplitMBBAt(CurMBB, BBI1))
451 const TargetInstrInfo *TII) {
458 !TII->AnalyzeBranch(*CurMBB, TBB, FBB, Cond, true))
[all...] |
| RegAllocPBQP.cpp | 130 const TargetInstrInfo *tii; member in class:__anon8133::RegAllocPBQP
644 tii = tm->getInstrInfo();
|
| VirtRegRewriter.cpp | 161 const TargetInstrInfo *TII;
178 AvailableSpills(const TargetRegisterInfo *tri, const TargetInstrInfo *tii)
179 : TRI(tri), TII(tii) {
292 const TargetInstrInfo *TII,
342 (TII->isLoadFromStackSlot(NewInsertLoc, FrameIdx) ||
343 TII->isTriviallyReMaterializable(NewInsertLoc)))
677 const TargetInstrInfo *TII,
686 TII->reMaterialize(MBB, MII, DestReg, 0, ReMatDefMI, *TRI);
791 if (!TII->isSafeToMoveRegClassDefs(RC)
[all...] |
| /external/llvm/lib/Target/Alpha/ |
| AlphaRegisterInfo.cpp | 41 AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii)
42 : AlphaGenRegisterInfo(Alpha::R26), TII(tii) {
104 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Alpha::LDA), Alpha::R30)
108 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Alpha::LDA), Alpha::R30)
171 TII.get(Alpha::LDAH), Alpha::R28)
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430RegisterInfo.cpp | 36 const TargetInstrInfo &tii)
37 : MSP430GenRegisterInfo(MSP430::PCW), TM(tm), TII(tii) {
122 if (Old->getOpcode() == TII.getCallFrameSetupOpcode()) {
124 TII.get(MSP430::SUB16ri), MSP430::SPW)
127 assert(Old->getOpcode() == TII.getCallFrameDestroyOpcode());
133 TII.get(MSP430::ADD16ri), MSP430::SPW)
145 } else if (I->getOpcode() == TII.getCallFrameDestroyOpcode()) {
151 BuildMI(MF, Old->getDebugLoc(), TII.get(MSP430::SUB16ri),
200 MI.setDesc(TII.get(MSP430::MOV16rr))
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCHazardRecognizers.cpp | 63 PPCHazardRecognizer970::PPCHazardRecognizer970(const TargetInstrInfo &tii)
64 : TII(tii) {
89 const MCInstrDesc &MCID = TII.get(Opcode);
|
| PPCRegisterInfo.cpp | 71 const TargetInstrInfo &tii)
75 Subtarget(ST), TII(tii) {
298 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg).addReg(StackReg).
302 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
304 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
307 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr))
382 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
387 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
391 BuildMI(MBB, II, dl, TII.get(PPC::LD), PPC::X0
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseRegisterInfo.h | 77 const ARMBaseInstrInfo &TII;
89 explicit ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
|
| Thumb1RegisterInfo.cpp | 43 Thumb1RegisterInfo::Thumb1RegisterInfo(const ARMBaseInstrInfo &tii,
45 : ARMBaseRegisterInfo(tii, sti) {
77 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRpci))
94 const TargetInstrInfo &TII,
116 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
119 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
121 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tRSB), LdReg))
130 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
170 int NumBytes, const TargetInstrInfo &TII,
230 TII, MRI, MIFlags)
[all...] |
| ARMBaseRegisterInfo.cpp | 57 ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
59 : ARMGenRegisterInfo(ARM::LR), TII(tii), STI(sti),
795 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
820 DebugLoc dl, const ARMBaseInstrInfo &TII,
825 Pred, PredReg, TII);
828 Pred, PredReg, TII);
863 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
868 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
[all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPURegisterInfo.cpp | 188 const TargetInstrInfo &tii) :
189 SPUGenRegisterInfo(SPU::R0), Subtarget(subtarget), TII(tii)
300 BuildMI(MBB, II, dl, TII.get(SPU::ILr32), tmpReg )
302 BuildMI(MBB, II, dl, TII.get(newOpcode), MI.getOperand(0).getReg())
|
| /external/llvm/lib/Target/XCore/ |
| XCoreRegisterInfo.cpp | 40 XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii)
41 : XCoreGenRegisterInfo(XCore::LR), TII(tii) {
148 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode))
153 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode), XCore::SP)
239 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
244 BuildMI(MBB, II, dl, TII.get(XCore::STW_3r))
250 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
260 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
265 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus)
[all...] |
| /external/llvm/lib/Target/Blackfin/ |
| BlackfinRegisterInfo.cpp | 38 const TargetInstrInfo &tii)
39 : BlackfinGenRegisterInfo(BF::RETS), Subtarget(st), TII(tii) {}
97 BuildMI(MBB, I, DL, TII.get(BF::ADDpp_imm7), Reg)
108 BuildMI(MBB, I, DL, TII.get(BF::ADDpp), Reg)
115 BuildMI(MBB, I, DL, TII.get(BF::ADD), Reg)
128 BuildMI(MBB, I, DL, TII.get(BF::LOADimm7), Reg).addImm(value);
133 BuildMI(MBB, I, DL, TII.get(BF::LOADuimm16), Reg).addImm(value);
138 BuildMI(MBB, I, DL, TII.get(BF::LOADimm16), Reg).addImm(value);
144 TII.get(BF::LOAD16i), getSubReg(Reg, BF::hi16)
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsRegisterInfo.cpp | 45 const TargetInstrInfo &tii)
46 : MipsGenRegisterInfo(Mips::RA), Subtarget(ST), TII(tii) {}
320 BuildMI(MBB, II, DL, TII.get(Mips::NOAT));
321 BuildMI(MBB, II, DL, TII.get(Mips::LUi), Mips::AT).addImm(ImmHi);
322 BuildMI(MBB, II, DL, TII.get(Mips::ADDu), Mips::AT).addReg(FrameReg)
327 BuildMI(MBB, ++II, MI.getDebugLoc(), TII.get(Mips::ATMACRO));
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGRRList.cpp | 285 const TargetInstrInfo *TII,
305 const MCInstrDesc Desc = TII->get(Opcode);
306 const TargetRegisterClass *RC = TII->getRegClass(Desc, Idx, TRI);
805 if (!TII->unfoldMemoryOperand(*DAG, N, NewNodes))
840 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86RegisterInfo.cpp | 54 const TargetInstrInfo &tii)
59 TM(tm), TII(tii) {
521 bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
542 if (Opcode == TII.getCallFrameSetupOpcode()) {
543 New = BuildMI(MF, DL, TII.get(getSUBriOpcode(Is64Bit, Amount)),
548 assert(Opcode == TII.getCallFrameDestroyOpcode());
555 New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
571 if (Opcode == TII.getCallFrameDestroyOpcode() && CalleeAmt) {
576 MachineInstr *New = BuildMI(MF, DL, TII.get(Opc), StackPtr
[all...] |
| /external/chromium/third_party/libjingle/source/talk/session/phone/testdata/ |
| voice.rtpdump | [all...] |
