| /external/llvm/test/CodeGen/Mips/ |
| unalignedload.ll | 15 ; CHECK-EL: lbu $[[R1:[0-9]+]], 6($[[R0]])
27 ; CHECK-EB: lbu $[[R3:[0-9]+]], 6($[[R1]])
|
| mips64intldst.ll | 68 ; CHECK-N64: lbu ${{[0-9]+}}, 0($[[R0]])
71 ; CHECK-N32: lbu ${{[0-9]+}}, 0($[[R0]])
|
| /external/llvm/test/MC/MBlaze/ |
| mblaze_memory.s | 9 # CHECK: lbu
12 lbu r1, r2, r3
|
| /external/llvm/test/MC/Disassembler/MBlaze/ |
| mblaze_memory.txt | 7 # CHECK: lbu r1, r2, r3
|
| /external/v8/src/mips/ |
| constants-mips.cc | 326 case LBU:
|
| disasm-mips.cc | 854 case LBU:
855 Format(instr, "lbu 'rt, 'imm16s('rs)");
|
| assembler-mips.cc | 1283 void Assembler::lbu(Register rd, const MemOperand& rs) { function in class:v8::internal::Assembler
[all...] |
| macro-assembler-mips.cc | [all...] |
| constants-mips.h | 231 LBU = ((4 << 3) + 4) << kOpcodeShift,
|
| assembler-mips.h | 624 void lbu(Register rd, const MemOperand& rs);
[all...] |
| simulator-mips.cc | [all...] |
| /external/llvm/lib/Target/MBlaze/Disassembler/ |
| MBlazeDisassembler.cpp | 56 MBlaze::LBU, MBlaze::LHU, MBlaze::LW, UNSUPPORTED, //30,31,32,33
358 case 0x0: return MBlaze::LBU;
473 case MBlaze::LBU: return decodeLBU(insn);
|
| /external/llvm/lib/Target/Mips/ |
| Mips64InstrInfo.td | 104 defm LBu64 : LoadM64<0x24, "lbu", zextloadi8>;
|
| MipsInstrInfo.td | 714 defm LBu : LoadM32<0x24, "lbu", zextloadi8>;
[all...] |
| /external/webkit/Source/JavaScriptCore/assembler/ |
| MacroAssemblerMIPS.h | 471 m_assembler.lbu(dest, address.base, address.offset);
476 lbu dest, (offset & 0xffff)(addrTemp)
480 m_assembler.lbu(dest, addrTempRegister, address.offset);
[all...] |
| MIPSAssembler.h | 413 void lbu(RegisterID rt, RegisterID rs, int offset) function in class:JSC::MIPSAssembler
|
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeInstrInfo.td | 446 def LBU : LoadM<0x30, 0x000, "lbu ">;
[all...] |
| /prebuilt/linux-x86/toolchain/i686-linux-glibc2.7-4.4.3/sysroot/usr/lib/gconv/ |
| IBM1364.so | |
| IBM933.so | |
| /external/webkit/Source/JavaScriptCore/ |
| ChangeLog-2010-05-24 | [all...] |
