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  /dalvik/vm/compiler/codegen/
Ralloc.h 40 static inline int dvmCompilerS2VReg(CompilationUnit *cUnit, int sReg)
42 assert(sReg != INVALID_SREG);
43 return DECODE_REG(dvmConvertSSARegToDalvik(cUnit, sReg));
53 * Get the "real" sreg number associated with an sReg slot. In general,
54 * sReg values passed through codegen are the SSA names created by
67 static inline bool dvmCompilerLiveOut(CompilationUnit *cUnit, int sReg)
94 extern void dvmCompilerMarkLive(CompilationUnit *cUnit, int reg, int sReg);
177 /* Clobber any temp associated with an sReg. Could be in either class */
178 extern void dvmCompilerClobberSReg(CompilationUnit *cUnit, int sReg);
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RallocUtil.cpp 30 #define SREG(c, s) ((c)->regLocation[(s)].sRegLow)
32 * Get the "real" sreg number associated with an sReg slot. In general,
33 * sReg values passed through codegen are the SSA names created by
67 regs[i].sReg = INVALID_SREG;
78 p[i].dirty, p[i].sReg,(int)p[i].defStart, (int)p[i].defEnd);
115 if (dvmCompilerS2VReg(cUnit, info2->sReg) <
116 dvmCompilerS2VReg(cUnit, info1->sReg))
119 dvmCompilerS2VReg(cUnit, info1->sReg) << 2,
130 dvmCompilerS2VReg(cUnit, info->sReg) << 2
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  /external/chromium/chrome/common/extensions/docs/examples/apps/hello-php/lib/lightopenid/
openid.php 30 * AX and SREG extensions are supported.
36 * If the server supports only SREG or OpenID 1.1, these are automaticaly
37 * mapped to SREG names, so that user doesn't have to know anything about the server.
54 , $ax = false, $sreg = false, $data;
212 # We ignore it for MyOpenID, as it breaks sreg if using OpenID 2.0
223 # Does the server advertise support for either AX or SREG?
225 $this->sreg = strpos($content, '<Type>http://openid.net/sreg/1.0</Type>') variable
226 || strpos($content, '<Type>http://openid.net/extensions/sreg/1.1</Type>');
246 # AX can be used only with OpenID 2.0, so checking only SREG
247 $this->sreg = strpos($content, '<Type>http:\/\/openid.net\/sreg\/1.0<\/Type>') variable
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  /dalvik/vm/compiler/codegen/arm/
ArchFactory.cpp 53 * Perform null-check on a register. sReg is the ssa register being checked,
55 * indicates that sReg has been checked before the check request is ignored.
57 static TGT_LIR *genNullCheck(CompilationUnit *cUnit, int sReg, int mReg,
61 if (dvmIsBitSet(cUnit->regPool->nullCheckedRegs, sReg)) {
64 dvmSetBit(cUnit->regPool->nullCheckedRegs, sReg);
CodegenCommon.cpp 338 * return the target Dalvik sReg[s] and convert the next to a
ArmLIR.h 109 int sReg; // Name of live value
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  /external/clang/include/clang/StaticAnalyzer/Core/PathSensitive/
MemRegion.h 296 SubRegion(const MemRegion* sReg, Kind k) : MemRegion(k), superRegion(sReg) {}
355 TypedRegion(const MemRegion* sReg, Kind k) : SubRegion(sReg, k) {}
375 TypedValueRegion(const MemRegion* sReg, Kind k) : TypedRegion(sReg, k) {}
403 CodeTextRegion(const MemRegion *sreg, Kind k) : TypedRegion(sreg, k) {}
417 FunctionTextRegion(const FunctionDecl *fd, const MemRegion* sreg)
418 : CodeTextRegion(sreg, FunctionTextRegionKind), FD(fd) {
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  /external/clang/lib/StaticAnalyzer/Core/
MemRegion.cpp 304 const MemRegion *sreg) {
307 ID.AddPointer(sreg);
353 const MemRegion *sReg) {
357 ID.AddPointer(sReg);
366 const MemRegion *sReg) {
368 ID.AddPointer(sReg);
377 const MemRegion *sReg) {
379 ID.AddPointer(sReg);
566 const MemRegion *sReg = 0;
569 sReg = getGlobalsRegion()
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  /external/llvm/lib/CodeGen/
RegisterScavenging.cpp 356 unsigned SReg = findSurvivorReg(I, Candidates, 25, UseMI);
359 if (!isAliasUsed(SReg)) {
360 DEBUG(dbgs() << "Scavenged register: " << TRI->getName(SReg) << "\n");
361 return SReg;
368 ScavengedReg = SReg;
372 if (!TRI->saveScavengerRegister(*MBB, I, UseMI, RC, SReg)) {
376 TII->storeRegToStackSlot(*MBB, I, SReg, true, ScavengingFrameIndex, RC,TRI);
381 TII->loadRegFromStackSlot(*MBB, UseMI, SReg, ScavengingFrameIndex, RC, TRI);
389 // ScavengedReg = SReg;
392 DEBUG(dbgs() << "Scavenged register (with spill): " << TRI->getName(SReg) <<
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VirtRegMap.h 216 /// @brief records virtReg is a split live interval from SReg.
217 void setIsSplitFromReg(unsigned virtReg, unsigned SReg) {
218 Virt2SplitMap[virtReg] = SReg;
VirtRegRewriter.cpp 533 unsigned SReg = *SR;
534 if (RegKills[SReg] && KillOps[SReg]->getParent() != &MI)
535 ResurrectConfirmedKill(SReg, TRI, RegKills, KillOps);
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  /external/v8/src/arm/
simulator-arm.cc 930 void Simulator::set_s_register(int sreg, unsigned int value) {
931 ASSERT((sreg >= 0) && (sreg < num_s_registers));
932 vfp_register[sreg] = value;
936 unsigned int Simulator::get_s_register(int sreg) const {
937 ASSERT((sreg >= 0) && (sreg < num_s_registers));
938 return vfp_register[sreg];
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simulator-arm.h 166 void set_s_register_from_float(int sreg, const float dbl);
167 float get_float_from_s_register(int sreg);
  /dalvik/vm/compiler/codegen/arm/Thumb/
Factory.cpp 577 OpSize size, int sReg)
580 * on base (which must have an associated sReg and MIR). If not
699 int sReg)
702 size, sReg);
707 int sReg)
710 kLong, sReg);
  /dalvik/vm/compiler/codegen/arm/Thumb2/
Factory.cpp 839 * on base (which must have an associated sReg and MIR). If not
844 OpSize size, int sReg)
869 -1, kWord, sReg);
961 int sReg)
964 size, sReg);
969 int sReg)
972 kLong, sReg);
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  /external/llvm/lib/Target/PowerPC/
PPCRegisterInfo.cpp 596 unsigned SReg;
598 SReg = findScratchRegister(II, RS, &PPC::GPRCRegClass, SPAdj);
600 SReg = PPC::R0;
603 BuildMI(MBB, II, dl, TII.get(PPC::LIS), SReg)
605 BuildMI(MBB, II, dl, TII.get(PPC::ORI), SReg)
606 .addReg(SReg, RegState::Kill)
627 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false);
  /dalvik/vm/compiler/codegen/x86/
X86LIR.h 70 int sReg; // Name of live value
  /dalvik/vm/mterp/x86-atom/
footer.S 167 subl $$1, sReg0 # sReg<- sReg--
239 movl %ecx, sReg0 # sReg<- methodToCall
  /external/qemu/
gdbstub.c 589 #define LOAD_SEG(index, sreg)\
591 if (tmp != env->segs[sreg].selector)\
592 cpu_x86_load_seg(env, sreg, tmp);
596 #define LOAD_SEG(index, sreg) do {} while(0)
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  /external/valgrind/main/VEX/priv/
guest_amd64_toIR.c     [all...]
guest_x86_toIR.c 487 static Int segmentGuestRegOffset ( UInt sreg )
489 switch (sreg) {
564 static IRExpr* getSReg ( UInt sreg )
566 return IRExpr_Get( segmentGuestRegOffset(sreg), Ity_I16 );
569 static void putSReg ( UInt sreg, IRExpr* e )
572 stmt( IRStmt_Put( segmentGuestRegOffset(sreg), e ) );
1398 Int sreg; local
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  /external/llvm/lib/Target/ARM/
ARMAsmPrinter.cpp 244 unsigned SReg = Reg - ARM::S0;
245 bool odd = SReg & 0x1;
246 unsigned Rx = 256 + (SReg >> 1);
251 OutStreamer.AddComment(Twine(SReg));
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  /external/qemu/target-arm/
translate.c 1105 int sreg; local
1106 sreg = reg * 2 + n;
1107 return vfp_reg_offset(0, sreg);
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  /external/llvm/lib/Target/ARM/AsmParser/
ARMAsmParser.cpp     [all...]

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