Lines Matching refs:writel
160 #undef writel
166 #define writel outl
323 writel(0x00000001, ioaddr + PCIBusCfg);
327 writel(virt_to_bus(w840private.rx_ring), ioaddr + RxRingPtr);
328 writel(virt_to_bus(w840private.tx_ring), ioaddr + TxRingPtr);
345 writel(0xE010, ioaddr + PCIBusCfg);
347 writel(0, ioaddr + RxStartDemand);
353 writel(0x1A0F5, ioaddr + IntrStatus);
354 writel(0x1A0F5, ioaddr + IntrEnable);
368 writel(intr_stat & 0x001ffff, ioaddr + IntrStatus);
382 writel(0, ioaddr + RxStartDemand);
531 writel(0, ioaddr + TxStartDemand);
569 writel(intr_stat & 0x0001ffff, ioaddr + IntrStatus);
600 writel(w840private.csr6 &= ~0x20FA, ioaddr + NetworkConfig);
666 writel(0x00000001, ioaddr + PCIBusCfg);
731 writel(EE_ChipSelect, ee_addr);
736 writel(dataval, ee_addr);
738 writel(dataval | EE_ShiftClk, ee_addr);
741 writel(EE_ChipSelect, ee_addr);
744 writel(EE_ChipSelect | EE_ShiftClk, ee_addr);
747 writel(EE_ChipSelect, ee_addr);
752 writel(0, ee_addr);
781 writel(MDIO_WRITE1, mdio_addr);
783 writel(MDIO_WRITE1 | MDIO_ShiftClk, mdio_addr);
801 writel(dataval, mdio_addr);
803 writel(dataval | MDIO_ShiftClk, mdio_addr);
808 writel(MDIO_EnbIn, mdio_addr);
811 writel(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr);
833 writel(dataval, mdio_addr);
835 writel(dataval | MDIO_ShiftClk, mdio_addr);
840 writel(MDIO_EnbIn, mdio_addr);
842 writel(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr);
887 writel(mc_filter[0], ioaddr + MulticastFilter0);
888 writel(mc_filter[1], ioaddr + MulticastFilter1);
891 writel(w840private.csr6, ioaddr + NetworkConfig);
