Lines Matching refs:reg
112 for (unsigned Reg = 1, RegE = tri_->getNumRegs(); Reg != RegE; ++Reg)
113 if (const LiveInterval *LI = r2iMap_.lookup(Reg)) {
119 for (unsigned Reg = 0, RegE = mri_->getNumVirtRegs(); Reg != RegE; ++Reg)
121 r2iMap_.lookup(TargetRegisterInfo::index2VirtReg(Reg))) {
140 unsigned Reg = MI.getOperand(MOIdx).getReg();
145 if (MO.getReg() == Reg && MO.isDef()) {
168 return DefMI->findRegisterDefOperandIdx(interval.reg) != -1;
179 DEBUG(dbgs() << "\t\tregister: " << PrintReg(interval.reg, tri_));
185 LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg);
229 bool PHIJoin = lv_->isPHIJoin(interval.reg);
326 } else if (lv_->isPHIJoin(interval.reg)) {
350 static bool isRegLiveIntoSuccessor(const MachineBasicBlock *MBB, unsigned Reg) {
355 if (succ->isLiveIn(Reg))
366 DEBUG(dbgs() << "\t\tregister: " << PrintReg(interval.reg, tri_));
394 if (mi->killsRegister(interval.reg, tri_)) {
399 int DefIdx = mi->findRegisterDefOperandIdx(interval.reg,false,false,tri_);
420 assert(!isAllocatable(interval.reg) && "Physregs shouldn't be live out!");
423 if (isReserved(interval.reg)) {
428 assert(isRegLiveIntoSuccessor(MBB, interval.reg) &&
429 "Unreserved reg not live-out?");
461 assert(TargetRegisterInfo::isPhysicalRegister(interval.reg) &&
463 assert((!isAllocatable(interval.reg) || MBB->getParent()->begin() ||
467 DEBUG(dbgs() << "\t\tlivein register: " << PrintReg(interval.reg, tri_));
491 if (mi->killsRegister(interval.reg, tri_)) {
496 } else if (mi->modifiesRegister(interval.reg, tri_)) {
516 if (isAllocatable(interval.reg) ||
517 !isRegLiveIntoSuccessor(MBB, interval.reg)) {
624 LiveInterval* LiveIntervals::createInterval(unsigned reg) {
625 float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ? HUGE_VALF : 0.0F;
626 return new LiveInterval(reg, Weight);
632 LiveInterval *NewLI = createInterval(li->reg);
643 assert(TargetRegisterInfo::isVirtualRegister(li->reg)
651 // Visit all instructions reading li->reg.
652 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(li->reg);
654 if (UseMI->isDebugValue() || !UseMI->readsVirtualRegister(li->reg))
681 LiveInterval NewLI(li->reg, 0);
758 MI->addRegisterDead(li->reg, tri_);
779 unsigned Reg = I->first;
780 if (TargetRegisterInfo::isPhysicalRegister(Reg))
782 if (mri_->reg_nodbg_empty(Reg))
786 // Every instruction that kills Reg corresponds to a live range end point.
795 MI->addRegisterKilled(Reg, NULL);
810 unsigned Reg = MO.getReg();
811 if (Reg == 0 || Reg == li.reg)
814 if (TargetRegisterInfo::isPhysicalRegister(Reg) && !isAllocatable(Reg))
844 // if it has one virtual reg use, though it had better be something like
850 ri = mri_->use_nodbg_begin(li.reg), re = mri_->use_nodbg_end();
864 if (ImpUse == (*SpillIs)[i]->reg)
937 LiveRange LiveIntervals::addLiveRangeToEndOfBlock(unsigned reg,
939 LiveInterval& Interval = getOrCreateInterval(reg);
1174 unsigned Reg = MO.getReg();
1179 if (!LIS.hasInterval(Reg) ||
1180 (TargetRegisterInfo::isPhysicalRegister(Reg) && LIS.isReserved(Reg)))
1183 LiveInterval* LI = &LIS.getInterval(Reg);
1224 unsigned Reg = MO.getReg();
1229 if (!LIS.hasInterval(Reg) ||
1230 (TargetRegisterInfo::isPhysicalRegister(Reg) && LIS.isReserved(Reg)))
1233 LiveInterval* LI = &LIS.getInterval(Reg);
1257 BR[LI->reg].Use = LR;
1265 BR[LI->reg].Dead = LR;
1267 BR[LI->reg].EC = LR;
1275 BR[LI->reg].Def = LR;
1281 void moveKillFlags(unsigned reg, SlotIndex OldIdx, SlotIndex newKillIdx) {
1283 if (!OldKillMI->killsRegister(reg))
1286 assert(OldKillMI->killsRegister(reg) && "Old 'kill' instr isn't a kill.");
1287 assert(!NewKillMI->killsRegister(reg) && "New kill instr is already a kill.");
1288 OldKillMI->clearRegisterKills(reg, &TRI);
1289 NewKillMI->addRegisterKilled(reg, &TRI);
1302 // Return the last use of reg between NewIdx and OldIdx.
1303 SlotIndex findLastUseBefore(unsigned Reg, SlotIndex OldIdx) {
1306 UI = MRI.use_nodbg_begin(Reg),
1323 SlotIndex LastUse = findLastUseBefore(LI->reg, OldIdx);
1325 moveKillFlags(LI->reg, NewIdx, LastUse);
1338 moveKillFlags(LI->reg, LR->end, NewIdx);
1400 assert((LR->start < NewIdx || BR[LI->reg].Def == LR) &&
1402 assert((BR[LI->reg].Use == 0 || BR[LI->reg].Use == LR) &&
1403 "If bundle has use for this reg it should be LR.");
1404 BR[LI->reg].Use = LR;
1408 SlotIndex LastUse = findLastUseBefore(LI->reg, OldIdx);
1409 moveKillFlags(LI->reg, OldIdx, LastUse);
1413 assert(BR[LI->reg].Dead == 0 && BR[LI->reg].Def == 0 &&
1414 "Bundle shouldn't be re-defining reg mid-range.");
1415 assert((BR[LI->reg].Use == 0 || BR[LI->reg].Use == LR) &&
1416 "Bundle shouldn't have different use range for same reg.");
1418 BR[LI->reg].Use = LR;
1423 assert(BR[LI->reg].Def == LR && "Reg should have def range.");
1424 assert(BR[LI->reg].Dead == 0 &&
1425 "Can't have def and dead def of same reg in a bundle.");
1427 BR[LI->reg].Dead = BR[LI->reg].Def;
1428 BR[LI->reg].Def = 0;
1439 assert(BR[LI->reg].Use == 0 &&
1440 "Bundle already has use range for reg.");
1441 moveKillFlags(LI->reg, LR->end, NewIdx);
1443 BR[LI->reg].Use = LR;
1445 assert(BR[LI->reg].Use != 0 &&
1446 "Bundle should already have a use range for reg.");
1487 // If there was an old dead-def of this reg, delete it.
1488 if (BR[LI->reg].Dead != 0) {
1489 LI->removeRange(*BR[LI->reg].Dead);
1490 BR[LI->reg].Dead = 0;
1492 assert(BR[LI->reg].Def == 0 &&
1496 BR[LI->reg].Def = LR;
1501 if (BR[LI->reg].Dead || BR[LI->reg].Def) {
1507 BR[LI->reg].Dead = LR;
1508 assert(BR[LI->reg].Use == LR &&
1512 BR[LI->reg].Use = 0;
