Lines Matching full:opc
243 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS);
566 SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL,
569 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
573 DAG.FoldConstantArithmetic(Opc, VT,
576 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
580 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
583 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
587 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
591 DAG.FoldConstantArithmetic(Opc, VT,
594 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode);
598 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
601 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1));
735 unsigned Opc = Op.getOpcode();
736 switch (Opc) {
802 unsigned Opc = Op.getOpcode();
803 if (TLI.isTypeDesirableForOp(Opc, VT))
842 DAG.getNode(Opc, dl, PVT, NN0, NN1));
860 unsigned Opc = Op.getOpcode();
861 Opc, VT))
872 if (Opc == ISD::SRA)
874 else if (Opc == ISD::SRL)
889 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1)));
904 unsigned Opc = Op.getOpcode();
905 if (TLI.isTypeDesirableForOp(Opc, VT))
933 unsigned Opc = Op.getOpcode();
934 if (TLI.isTypeDesirableForOp(Opc, VT))
2819 unsigned Opc = N.getOpcode();
2820 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL)
2839 if (Opc == ISD::AND) {
2857 } else if (Opc == ISD::SHL) {
2865 } else { // Opc == ISD::SRL
4930 unsigned Opc = N->getOpcode();
4943 if (Opc == ISD::SIGN_EXTEND_INREG) {
4946 } else if (Opc == ISD::SRL) {
6862 unsigned Opc = Value.getOpcode();
6869 if (Opc == ISD::OR) {
6885 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) ||
6902 if (Opc == ISD::AND)
6911 !(TLI.isOperationLegalOrCustom(Opc, NewVT) &&
6926 if (Opc == ISD::AND)
6947 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD,
