Lines Matching refs:ISD
158 ISD::NodeType ExtType);
251 SDValue N3, ISD::CondCode CC,
253 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
392 if (Op.getOpcode() == ISD::FNEG) return 2;
402 case ISD::ConstantFP:
406 case ISD::FADD:
412 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType()))
422 case ISD::FSUB:
429 case ISD::FMUL:
430 case ISD::FDIV:
441 case ISD::FP_EXTEND:
442 case ISD::FP_ROUND:
443 case ISD::FSIN:
454 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
462 case ISD::ConstantFP: {
467 case ISD::FADD:
475 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
480 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
484 case ISD::FSUB:
494 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
497 case ISD::FMUL:
498 case ISD::FDIV:
516 case ISD::FP_EXTEND:
517 case ISD::FSIN:
521 case ISD::FP_ROUND:
522 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(),
537 if (N.getOpcode() == ISD::SETCC) {
543 if (N.getOpcode() == ISD::SELECT_CC &&
544 N.getOperand(2).getOpcode() == ISD::Constant &&
545 N.getOperand(3).getOpcode() == ISD::Constant &&
702 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0));
723 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
724 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
725 : ISD::EXTLOAD)
738 case ISD::AssertSext:
739 return DAG.getNode(ISD::AssertSext, dl, PVT,
742 case ISD::AssertZext:
743 return DAG.getNode(ISD::AssertZext, dl, PVT,
746 case ISD::Constant: {
748 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
753 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT))
755 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op);
759 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT))
771 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp,
841 return DAG.getNode(ISD::TRUNCATE, dl, VT,
872 if (Opc == ISD::SRA)
874 else if (Opc == ISD::SRL)
888 return DAG.getNode(ISD::TRUNCATE, dl, VT,
947 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
948 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
949 : ISD::EXTLOAD)
956 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD);
1036 assert(N->getOpcode() != ISD::DELETED_NODE &&
1037 RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
1089 case ISD::TokenFactor: return visitTokenFactor(N);
1090 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
1091 case ISD::ADD: return visitADD(N);
1092 case ISD::SUB: return visitSUB(N);
1093 case ISD::ADDC: return visitADDC(N);
1094 case ISD::SUBC: return visitSUBC(N);
1095 case ISD::ADDE: return visitADDE(N);
1096 case ISD::SUBE: return visitSUBE(N);
1097 case ISD::MUL: return visitMUL(N);
1098 case ISD::SDIV: return visitSDIV(N);
1099 case ISD::UDIV: return visitUDIV(N);
1100 case ISD::SREM: return visitSREM(N);
1101 case ISD::UREM: return visitUREM(N);
1102 case ISD::MULHU: return visitMULHU(N);
1103 case ISD::MULHS: return visitMULHS(N);
1104 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
1105 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
1106 case ISD::SMULO: return visitSMULO(N);
1107 case ISD::UMULO: return visitUMULO(N);
1108 case ISD::SDIVREM: return visitSDIVREM(N);
1109 case ISD::UDIVREM: return visitUDIVREM(N);
1110 case ISD::AND: return visitAND(N);
1111 case ISD::OR: return visitOR(N);
1112 case ISD::XOR: return visitXOR(N);
1113 case ISD::SHL: return visitSHL(N);
1114 case ISD::SRA: return visitSRA(N);
1115 case ISD::SRL: return visitSRL(N);
1116 case ISD::CTLZ: return visitCTLZ(N);
1117 case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N);
1118 case ISD::CTTZ: return visitCTTZ(N);
1119 case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N);
1120 case ISD::CTPOP: return visitCTPOP(N);
1121 case ISD::SELECT: return visitSELECT(N);
1122 case ISD::SELECT_CC: return visitSELECT_CC(N);
1123 case ISD::SETCC: return visitSETCC(N);
1124 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
1125 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
1126 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
1127 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
1128 case ISD::TRUNCATE: return visitTRUNCATE(N);
1129 case ISD::BITCAST: return visitBITCAST(N);
1130 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
1131 case ISD::FADD: return visitFADD(N);
1132 case ISD::FSUB: return visitFSUB(N);
1133 case ISD::FMUL: return visitFMUL(N);
1134 case ISD::FDIV: return visitFDIV(N);
1135 case ISD::FREM: return visitFREM(N);
1136 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
1137 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
1138 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
1139 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
1140 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
1141 case ISD::FP_ROUND: return visitFP_ROUND(N);
1142 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
1143 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
1144 case ISD::FNEG: return visitFNEG(N);
1145 case ISD::FABS: return visitFABS(N);
1146 case ISD::BRCOND: return visitBRCOND(N);
1147 case ISD::BR_CC: return visitBR_CC(N);
1148 case ISD::LOAD: return visitLOAD(N);
1149 case ISD::STORE: return visitSTORE(N);
1150 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
1151 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
1152 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
1153 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
1154 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N);
1155 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
1156 case ISD::MEMBARRIER: return visitMEMBARRIER(N);
1166 assert(N->getOpcode() != ISD::DELETED_NODE &&
1169 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
1170 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
1184 case ISD::ADD:
1185 case ISD::SUB:
1186 case ISD::MUL:
1187 case ISD::AND:
1188 case ISD::OR:
1189 case ISD::XOR:
1192 case ISD::SHL:
1193 case ISD::SRA:
1194 case ISD::SRL:
1197 case ISD::SIGN_EXTEND:
1198 case ISD::ZERO_EXTEND:
1199 case ISD::ANY_EXTEND:
1202 case ISD::LOAD:
1273 case ISD::EntryToken:
1279 case ISD::TokenFactor:
1311 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
1346 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() &&
1349 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT,
1350 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT,
1352 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT,
1354 return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
1374 if (N0.getOpcode() == ISD::UNDEF)
1376 if (N1.getOpcode() == ISD::UNDEF)
1380 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C);
1383 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0);
1390 GA->getOpcode() == ISD::GlobalAddress)
1395 if (N1C && N0.getOpcode() == ISD::SUB)
1397 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1402 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1);
1406 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
1408 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1));
1410 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
1412 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1));
1414 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
1417 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
1420 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1422 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1425 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1427 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1430 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
1431 N1.getOperand(0).getOpcode() == ISD::SUB &&
1437 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
1444 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1445 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10),
1446 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11));
1464 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1);
1469 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) {
1473 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) {
1479 if (N1.getOpcode() == ISD::SHL &&
1480 N1.getOperand(0).getOpcode() == ISD::SUB)
1484 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0,
1485 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1488 if (N0.getOpcode() == ISD::SHL &&
1489 N0.getOperand(0).getOpcode() == ISD::SUB)
1493 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1,
1494 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1498 if (N1.getOpcode() == ISD::AND) {
1508 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0);
1513 if (N0.getOpcode() == ISD::SIGN_EXTEND &&
1515 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) {
1517 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
1518 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt);
1533 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N1),
1534 DAG.getNode(ISD::CARRY_FALSE,
1539 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1543 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
1557 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1),
1558 DAG.getNode(ISD::CARRY_FALSE,
1574 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(),
1578 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1579 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N0, N1);
1591 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
1595 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT,
1606 ConstantSDNode *N1C1 = N1.getOpcode() != ISD::ADD ? 0 :
1622 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C);
1625 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0,
1629 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
1631 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0))
1634 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1637 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1640 if (N1.getOpcode() == ISD::ADD && N0C && N1C1) {
1642 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, NewC,
1646 if (N0.getOpcode() == ISD::ADD &&
1647 (N0.getOperand(1).getOpcode() == ISD::SUB ||
1648 N0.getOperand(1).getOpcode() == ISD::ADD) &&
1653 if (N0.getOpcode() == ISD::ADD &&
1654 N0.getOperand(1).getOpcode() == ISD::ADD &&
1656 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1659 if (N0.getOpcode() == ISD::SUB &&
1660 N0.getOperand(1).getOpcode() == ISD::SUB &&
1662 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1666 if (N0.getOpcode() == ISD::UNDEF)
1668 if (N1.getOpcode() == ISD::UNDEF)
1675 if (N1C && GA->getOpcode() == ISD::GlobalAddress)
1698 return CombineTo(N, DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1),
1699 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(),
1705 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(),
1710 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(),
1715 return CombineTo(N, DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0),
1716 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(),
1728 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1729 return DAG.getNode(ISD::SUBC, N->getDebugLoc(), N->getVTList(), N0, N1);
1748 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1752 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C);
1755 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0);
1761 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1765 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1773 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1775 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1780 if (N1C && N0.getOpcode() == ISD::SHL &&
1782 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1785 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1794 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
1797 } else if (N1.getOpcode() == ISD::SHL &&
1804 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1806 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1812 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
1814 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1815 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT,
1817 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT,
1821 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1);
1843 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C);
1849 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1855 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(),
1870 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
1876 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN,
1879 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL);
1882 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD,
1891 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1903 if (N0.getOpcode() == ISD::UNDEF)
1906 if (N1.getOpcode() == ISD::UNDEF)
1927 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C);
1930 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
1934 if (N1.getOpcode() == ISD::SHL) {
1938 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT,
1944 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add);
1955 if (N0.getOpcode() == ISD::UNDEF)
1958 if (N1.getOpcode() == ISD::UNDEF)
1973 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C);
1978 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1);
1984 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1);
1988 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1990 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
1997 if (N0.getOpcode() == ISD::UNDEF)
2000 if (N1.getOpcode() == ISD::UNDEF)
2015 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C);
2018 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0,
2021 if (N1.getOpcode() == ISD::SHL) {
2025 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1,
2029 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add);
2037 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1);
2041 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
2043 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
2050 if (N0.getOpcode() == ISD::UNDEF)
2053 if (N1.getOpcode() == ISD::UNDEF)
2071 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0,
2075 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2084 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2085 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
2086 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1);
2087 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2088 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2090 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2111 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2120 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2121 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0);
2122 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1);
2123 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2124 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2126 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2190 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
2202 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2203 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0));
2204 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1));
2205 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2207 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2209 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2211 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2220 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
2232 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2233 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0));
2234 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1));
2235 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2237 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2239 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2241 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2253 return DAG.getNode(ISD::SADDO, N->getDebugLoc(), N->getVTList(),
2263 return DAG.getNode(ISD::UADDO, N->getDebugLoc(), N->getVTList(),
2270 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
2277 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
2302 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
2303 N0.getOpcode() == ISD::SIGN_EXTEND ||
2305 (N0.getOpcode() == ISD::ANY_EXTEND &&
2307 (N0.getOpcode() == ISD::TRUNCATE &&
2325 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
2326 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
2343 if ((N0.getOpcode() == ISD::BITCAST || N0.getOpcode() == ISD::SCALAR_TO_VECTOR)
2365 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG &&
2366 N0.getOperand(1).getOpcode() == ISD::UNDEF &&
2367 N1.getOperand(1).getOpcode() == ISD::UNDEF) {
2416 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2420 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C);
2423 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0);
2432 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1);
2436 if (N1C && N0.getOpcode() == ISD::OR)
2441 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2446 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(),
2465 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
2466 N0.getOperand(0).getOpcode() == ISD::LOAD) ||
2467 N0.getOpcode() == ISD::LOAD) {
2468 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ?
2503 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD,
2515 case ISD::EXTLOAD: B = CanZextLoadProfitably; break;
2516 case ISD::ZEXTLOAD:
2517 case ISD::NON_EXTLOAD: B = true; break;
2524 if (Load->getExtensionType() == ISD::EXTLOAD) {
2525 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD,
2543 ISD
2544 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2549 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) {
2550 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
2556 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
2557 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(),
2563 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
2564 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
2572 Op1 = ISD::getSetCCSwappedOperands(Op1);
2577 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
2578 if (Result != ISD::SETCC_INVALID &&
2598 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
2607 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2608 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
2619 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
2629 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2630 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
2645 if (N1C && (N0.getOpcode() == ISD::LOAD ||
2646 (N0.getOpcode() == ISD::ANY_EXTEND &&
2647 N0.getOperand(0).getOpcode() == ISD::LOAD))) {
2648 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND;
2652 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
2660 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2664 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy,
2678 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2691 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType,
2700 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy,
2726 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
2732 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
2734 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL)
2736 if (N0.getOpcode() == ISD::AND) {
2746 if (N1.getOpcode() == ISD::AND) {
2756 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
2758 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
2773 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) {
2784 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) {
2805 SDValue Res = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, N00);
2807 Res = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Res,
2820 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL)
2839 if (Opc == ISD::AND) {
2843 if (N0.getOpcode() != ISD::SRL)
2851 if (N0.getOpcode() != ISD::SHL)
2857 } else if (Opc == ISD::SHL) {
2865 } else { // Opc == ISD::SRL
2892 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
2899 if (N0.getOpcode() != ISD::OR)
2904 if (N1.getOpcode() == ISD::OR) {
2925 if (N00.getOpcode() != ISD::OR)
2939 SDValue BSwap = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT,
2945 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT))
2946 return DAG.getNode(ISD::ROTL, N->getDebugLoc(), VT, BSwap, ShAmt);
2947 else if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT))
2948 return DAG.getNode(ISD::ROTR, N->getDebugLoc(), VT, BSwap, ShAmt);
2949 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT,
2950 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, BSwap, ShAmt),
2951 DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, BSwap, ShAmt));
2970 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) {
2976 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C);
2979 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0);
2999 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1);
3004 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
3008 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3009 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
3011 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1));
3015 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
3016 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
3023 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
3024 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(),
3032 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
3033 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(),
3041 Op1 = ISD::getSetCCSwappedOperands(Op1);
3046 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
3047 if (Result != ISD::SETCC_INVALID &&
3061 if (N0.getOpcode() == ISD::AND &&
3062 N1.getOpcode() == ISD::AND &&
3063 N0.getOperand(1).getOpcode() == ISD::Constant &&
3064 N1.getOperand(1).getOpcode() == ISD::Constant &&
3076 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
3078 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X,
3097 if (Op.getOpcode() == ISD::AND) {
3106 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
3123 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT);
3124 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
3145 if (RHSShift.getOpcode() == ISD::SHL) {
3158 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
3159 RHSShiftAmt.getOpcode() == ISD::Constant) {
3167 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt);
3169 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt);
3184 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT));
3197 if (RHSShiftAmt.getOpcode() == ISD::SUB &&
3203 return DAG.getNode(ISD::ROTL, DL, VT,
3206 return DAG.getNode(ISD::ROTR, DL, VT,
3214 if (LHSShiftAmt.getOpcode() == ISD::SUB &&
3220 return DAG.getNode(ISD::ROTR, DL, VT,
3223 return DAG.getNode(ISD::ROTL, DL, VT,
3230 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
3231 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
3232 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
3233 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) &&
3234 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
3235 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
3236 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
3237 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) {
3240 if (RExtOp0.getOpcode() == ISD::SUB &&
3249 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
3254 } else if (LExtOp0.getOpcode() == ISD::SUB &&
3263 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT,
3289 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
3292 if (N0.getOpcode() == ISD::UNDEF)
3294 if (N1.getOpcode() == ISD::UNDEF)
3298 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C);
3301 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
3306 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1);
3313 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
3320 case ISD::SETCC:
3322 case ISD::SELECT_CC:
3330 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
3334 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V,
3337 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V);
3342 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3345 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3346 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
3347 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
3354 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3357 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3358 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
3359 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
3365 if (N1C && N0.getOpcode() == ISD::XOR) {
3369 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1),
3373 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0),
3409 case ISD::OR:
3410 case ISD::XOR:
3413 case ISD::AND:
3416 case ISD::ADD:
3417 if (N->getOpcode() != ISD::SHL)
3433 if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
3434 BinOpLHSVal->getOpcode() != ISD::SRA &&
3435 BinOpLHSVal->getOpcode() != ISD::SRL) ||
3445 if (N->getOpcode() == ISD::SRA) {
3475 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C);
3486 if (N0.getOpcode() == ISD::UNDEF)
3493 if (N1.getOpcode() == ISD::TRUNCATE &&
3494 N1.getOperand(0).getOpcode() == ISD::AND &&
3502 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
3503 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT,
3504 DAG.getNode(ISD::TRUNCATE,
3515 if (N1C && N0.getOpcode() == ISD::SHL &&
3516 N0.getOperand(1).getOpcode() == ISD::Constant) {
3521 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
3530 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND ||
3531 N0.getOpcode() == ISD::ANY_EXTEND ||
3532 N0.getOpcode() == ISD::SIGN_EXTEND) &&
3533 N0.getOperand(0).getOpcode() == ISD::SHL &&
3543 return DAG.getNode(ISD::SHL, N0->getDebugLoc(), VT,
3554 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse() &&
3555 N0.getOperand(1).getOpcode() == ISD::Constant) {
3564 Shift = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
3568 Shift = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
3571 return DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, Shift,
3576 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) {
3582 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
3605 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C);
3620 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
3627 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT)))
3628 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
3633 if (N1C && N0.getOpcode() == ISD::SRA) {
3637 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0),
3647 if (N0.getOpcode() == ISD::SHL) {
3663 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
3664 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
3669 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT,
3671 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT,
3673 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(),
3680 if (N1.getOpcode() == ISD::TRUNCATE &&
3681 N1.getOperand(0).getOpcode() == ISD::AND &&
3689 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
3690 DAG.getNode(ISD::AND, N->getDebugLoc(),
3692 DAG.getNode(ISD::TRUNCATE,
3701 if (N0.getOpcode() == ISD::TRUNCATE &&
3702 (N0.getOperand(0).getOpcode() == ISD::SRL ||
3703 N0.getOperand(0).getOpcode() == ISD::SRA) &&
3716 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), LargeVT,
3718 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, SRA);
3729 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1);
3750 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C);
3766 if (N1C && N0.getOpcode() == ISD::SRL &&
3767 N0.getOperand(1).getOpcode() == ISD::Constant) {
3772 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
3777 if (N1C && N0.getOpcode() == ISD::TRUNCATE &&
3778 N0.getOperand(0).getOpcode() == ISD::SRL &&
3790 return DAG.getNode(ISD::TRUNCATE, N0->getDebugLoc(), VT,
3791 DAG.getNode(ISD::SRL, N0->getDebugLoc(), InnerShiftVT,
3798 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 &&
3801 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
3807 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
3813 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) {
3815 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT,
3819 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift);
3826 if (N0.getOpcode() == ISD::SRA)
3827 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1);
3831 if (N1C && N0.getOpcode() == ISD::CTLZ &&
3855 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op,
3860 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
3866 if (N1.getOpcode() == ISD::TRUNCATE &&
3867 N1.getOperand(0).getOpcode() == ISD::AND &&
3875 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
3876 DAG.getNode(ISD::AND, N->getDebugLoc(),
3878 DAG.getNode(ISD::TRUNCATE,
3920 if (Use->getOpcode() == ISD::BRCOND)
3922 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) {
3925 if (Use->getOpcode() == ISD::BRCOND)
3939 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0);
3949 return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0);
3959 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0);
3969 return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0);
3979 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0);
4004 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
4013 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0,
4015 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0,
4019 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode);
4020 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode);
4026 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2);
4032 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1);
4036 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
4040 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
4044 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
4051 if (N0.getOpcode() == ISD::SETCC) {
4056 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) &&
4057 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT))
4058 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT,
4073 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
4092 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC)
4093 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(),
4130 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) {
4131 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
4132 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
4153 if (User->getOpcode() == ISD::CopyToReg)
4162 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) {
4177 ISD::NodeType ExtType) {
4192 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0),
4203 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0);
4207 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
4208 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT,
4211 if (N0.getOpcode() == ISD::TRUNCATE) {
4242 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op);
4247 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
4251 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
4254 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op);
4256 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op);
4257 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op,
4266 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4268 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) {
4272 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
4275 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
4282 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4286 ISD::SIGN_EXTEND);
4293 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
4294 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
4298 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) {
4299 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
4307 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4316 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
4317 N0.getOpcode() == ISD::XOR) &&
4319 N0.getOperand(1).getOpcode() == ISD::Constant &&
4320 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()) &&
4323 if (LN0->getExtensionType() != ISD::ZEXTLOAD) {
4327 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND,
4330 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, LN0->getDebugLoc(), VT,
4341 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
4347 ISD::SIGN_EXTEND);
4353 if (N0.getOpcode() == ISD::SETCC) {
4402 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT)))
4403 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
4412 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
4414 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
4426 if (N->getOpcode() == ISD::TRUNCATE) {
4432 if (N->getOpcode() != ISD::SETCC || N->getValueType(0) != MVT::i1 ||
4433 cast<CondCodeSDNode>(N->getOperand(2))->get() != ISD::SETNE)
4463 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
4466 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
4467 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT,
4486 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, Op);
4488 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
4496 if (N0.getOpcode() == ISD::TRUNCATE) {
4510 if (N0.getOpcode() == ISD::TRUNCATE &&
4511 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) {
4528 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op);
4530 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
4538 if (N0.getOpcode() == ISD::AND &&
4539 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
4540 N0.getOperand(1).getOpcode() == ISD::Constant &&
4546 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X);
4548 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
4552 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4560 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4562 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
4566 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
4569 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
4576 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4581 ISD::ZERO_EXTEND);
4588 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
4589 N0.getOpcode() == ISD::XOR) &&
4591 N0.getOperand(1).getOpcode() == ISD::Constant &&
4592 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()) &&
4595 if (LN0->getExtensionType() != ISD::SEXTLOAD) {
4599 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::ZERO_EXTEND,
4602 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT,
4613 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
4619 ISD::ZERO_EXTEND);
4627 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
4628 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
4632 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) {
4633 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
4641 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(),
4648 if (N0.getOpcode() == ISD::SETCC) {
4662 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4666 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
4682 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4684 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
4697 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
4699 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
4703 if (N0.getOpcode() == ISD::SHL) {
4717 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt);
4720 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)),
4733 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0);
4737 if (N0.getOpcode() == ISD::ANY_EXTEND ||
4738 N0.getOpcode() == ISD::ZERO_EXTEND ||
4739 N0.getOpcode() == ISD::SIGN_EXTEND)
4744 if (N0.getOpcode() == ISD::TRUNCATE) {
4758 if (N0.getOpcode() == ISD::TRUNCATE) {
4763 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp);
4764 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp);
4769 if (N0.getOpcode() == ISD::AND &&
4770 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
4771 N0.getOperand(1).getOpcode() == ISD::Constant &&
4776 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X);
4778 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X);
4782 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4790 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4792 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
4796 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI);
4799 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
4806 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4810 ISD::ANY_EXTEND);
4818 if (N0.getOpcode() == ISD::LOAD &&
4819 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
4830 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4836 if (N0.getOpcode() == ISD::SETCC) {
4886 case ISD::Constant: {
4896 case ISD::OR:
4897 case ISD::XOR:
4904 case ISD::SRL:
4917 ISD::SRL, V.getDebugLoc(), V.getValueType(),
4932 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
4943 if (Opc == ISD::SIGN_EXTEND_INREG) {
4944 ExtType = ISD::SEXTLOAD;
4946 } else if (Opc == ISD::SRL) {
4948 ExtType = ISD::ZEXTLOAD;
4966 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
4993 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() &&
5025 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(),
5031 if (ExtType == ISD::NON_EXTLOAD)
5053 Result = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT,
5070 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
5071 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1);
5078 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
5080 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
5087 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
5090 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT)))
5091 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1);
5112 if (N0.getOpcode() == ISD::SRL) {
5119 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT,
5125 if (ISD::isEXTLoad(N0.getNode()) &&
5126 ISD::isUNINDEXEDLoad(N0.getNode()) &&
5129 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
5131 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
5142 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
5146 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
5148 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
5160 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) {
5164 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
5181 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0);
5183 if (N0.getOpcode() == ISD::TRUNCATE)
5184 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
5186 if (N0.getOpcode() == ISD::ZERO_EXTEND ||
5187 N0.getOpcode() == ISD::SIGN_EXTEND ||
5188 N0.getOpcode() == ISD::ANY_EXTEND) {
5195 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
5212 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5231 SDValue V = DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
5234 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
5250 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter);
5270 if (Elt.getOpcode() != ISD::MERGE_VALUES)
5278 assert(N->getOpcode() == ISD::BUILD_PAIR);
5282 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() ||
5288 if (ISD::isNON_EXTLoad(LD2) &&
5300 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)))
5318 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
5322 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
5323 N0.getOperand(i).getOpcode() != ISD::Constant &&
5324 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
5338 SDValue Res = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, N0);
5354 if (N0.getOpcode() == ISD::BITCAST)
5355 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT,
5360 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
5363 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) {
5376 DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
5386 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(VT)) ||
5387 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(VT))) &&
5389 SDValue NewConv = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), VT,
5394 if (N0.getOpcode() == ISD::FNEG)
5395 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
5397 assert(N0.getOpcode() == ISD::FABS);
5398 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
5406 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
5412 SDValue X = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
5419 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X);
5424 X = DAG.getNode(ISD::SRL, X.getDebugLoc(),
5428 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
5433 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT,
5437 SDValue Cst = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
5439 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT,
5443 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst);
5448 if (N0.getOpcode() == ISD::BUILD_PAIR) {
5483 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR)
5484 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
5485 DAG.getNode(ISD::BITCAST, BV->getDebugLoc(),
5494 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op);
5495 Ops.push_back(DAG.getNode(ISD::BITCAST, BV->getDebugLoc(),
5499 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
5542 if (Op.getOpcode() == ISD::UNDEF) continue;
5556 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
5562 bool isS2V = ISD::isScalarToVector(BV);
5569 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
5583 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
5593 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
5612 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1);
5615 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0);
5621 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
5623 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0,
5626 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
5628 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1,
5633 N0.getOpcode() == ISD::FADD && N0.getNode()->hasOneUse() &&
5635 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0),
5636 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5657 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1);
5667 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
5668 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1);
5672 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0,
5679 if (N1.getOpcode() == ISD::FADD) {
5711 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1);
5714 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0);
5721 ISD::isBuildVectorAllZeros(N1.getNode()))
5725 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0);
5728 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
5729 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0);
5739 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5747 N1CFP && N0.getOpcode() == ISD::FMUL &&
5749 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0),
5750 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5772 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1);
5786 // TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT) ||
5787 TLI.isOperationLegal(llvm::ISD::ConstantFP, VT) ||
5789 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0,
5801 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT,
5819 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1);
5832 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1);
5839 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT))
5840 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
5842 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
5843 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT,
5844 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0));
5851 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
5852 N0.getOpcode() == ISD::FCOPYSIGN)
5853 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
5857 if (N1.getOpcode() == ISD::FABS)
5858 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
5861 if (N1.getOpcode() == ISD::FCOPYSIGN)
5862 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
5867 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
5868 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
5884 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
5885 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
5889 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) &&
5890 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) {
5893 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
5909 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
5910 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
5914 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) &&
5915 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) {
5918 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
5931 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0);
5943 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0);
5956 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1);
5959 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
5963 if (N0.getOpcode() == ISD::FP_ROUND) {
5967 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0),
5972 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
5973 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT,
5976 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
5992 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round);
6005 N->use_begin()->getOpcode() == ISD::FP_ROUND)
6010 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0);
6014 if (N0.getOpcode() == ISD::FP_ROUND
6019 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT,
6021 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In);
6025 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
6027 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
6029 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
6037 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(),
6056 if (!TLI.isFNegFree(VT) && N0.getOpcode() == ISD::BITCAST &&
6063 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int,
6066 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
6081 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
6083 if (N0.getOpcode() == ISD::FABS)
6087 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
6088 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0));
6093 N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() &&
6099 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int,
6102 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
6123 if (N1.getOpcode() == ISD::SETCC &&
6124 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) {
6125 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
6130 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) ||
6131 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) &&
6133 N1.getOperand(0).getOpcode() == ISD::SRL))) {
6135 if (N1.getOpcode() == ISD::TRUNCATE) {
6161 if (Op0.getOpcode() == ISD::AND &&
6162 Op1.getOpcode() == ISD::Constant) {
6165 if (AndOp1.getOpcode() == ISD::Constant) {
6174 ISD::SETNE);
6176 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
6203 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) {
6220 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
6225 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) {
6229 Op0.getOpcode() == ISD::XOR) {
6240 Equal ? ISD::SETEQ : ISD::SETNE);
6246 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
6273 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
6274 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
6301 if (N->getOpcode() == ISD::ADD) {
6309 } else if (N->getOpcode() == ISD::SUB) {
6340 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
6341 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
6348 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
6349 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
6359 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
6366 ISD::MemIndexedMode AM = ISD::UNINDEXED;
6471 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
6472 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
6479 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
6480 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
6495 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
6500 ISD::MemIndexedMode AM = ISD::UNINDEXED;
6527 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
6648 if (ISD::isNormalLoad(N) && !LD->isVolatile()) {
6649 if (ISD::isNON_TRUNCStore(Chain.getNode())) {
6678 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
6694 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
6721 if (V->getOpcode() != ISD::AND ||
6723 !ISD::isNormalLoad(V->getOperand(0).getNode()))
6734 else if (Chain->getOpcode() != ISD::TokenFactor)
6815 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal,
6830 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(),
6836 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal);
6869 if (Opc == ISD::OR) {
6885 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) ||
6886 Value.getOperand(1).getOpcode() != ISD::Constant)
6890 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
6902 if (Opc == ISD::AND)
6926 if (Opc == ISD::AND)
6939 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(),
6976 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) &&
6990 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) ||
6991 !TLI.isOperationLegal(ISD::STORE, IntVT) ||
6992 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) ||
6993 ISD::STORE, VT))
7033 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() &&
7041 TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))
7048 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed())
7057 if (Value.getOpcode() != ISD::TargetConstantFP) {
7067 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
7078 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
7087 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
7104 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr,
7111 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
7158 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
7215 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
7235 if (InVal.getOpcode() == ISD::UNDEF)
7241 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
7253 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
7256 } else if (InVec.getOpcode() == ISD::UNDEF) {
7270 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) :
7271 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal);
7276 return DAG.getNode(ISD::BUILD_VECTOR, dl,
7286 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
7306 if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE
7326 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(), NVT,
7350 if (InVec.getOpcode() == ISD::BITCAST) {
7367 if (ISD::isNormalLoad(InVec.getNode())) {
7369 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
7371 ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
7396 if (InVec.getOpcode() == ISD::BITCAST) {
7403 if (ISD::isNormalLoad(InVec.getNode())) {
7426 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT))
7440 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr,
7455 ISD::LoadExtType ExtType = TLI.isLoadExtLegal(ISD::ZEXTLOAD, LVT)
7456 ? ISD::ZEXTLOAD : ISD::EXTLOAD;
7468 Load = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Load);
7470 Load = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), NVT, Load);
7503 if (In.getOpcode() == ISD::UNDEF) continue;
7506 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND;
7507 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND;
7565 assert((Cast.getOpcode() == ISD::ANY_EXTEND ||
7566 Cast.getOpcode() == ISD::ZERO_EXTEND ||
7567 Cast.getOpcode() == ISD::UNDEF) && "Invalid cast opcode");
7569 if (Cast.getOpcode() == ISD::UNDEF)
7588 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
7594 return DAG.getNode(ISD::BITCAST, dl, N->getValueType(0), BV);
7603 !TLI.isOperationLegalOrCustom(ISD::VECTOR_SHUFFLE, VT))
7609 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
7613 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
7639 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
7674 VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT,
7717 if (V->getOpcode() == ISD::INSERT_SUBVECTOR) {
7739 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(), NVT,
7757 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
7775 if (N0.getOpcode() == ISD::UNDEF) {
7792 if (N1.getOpcode() == ISD::UNDEF) {
7815 if (V->getOpcode() == ISD::BITCAST) {
7822 if (V->getOpcode() == ISD::BUILD_VECTOR) {
7828 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
7851 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG &&
7852 N1.getOpcode() == ISD::UNDEF) {
7857 if (N0.getOperand(1).getOpcode() != ISD::UNDEF)
7890 case ISD::ATOMIC_CMP_SWAP:
7891 case ISD::ATOMIC_SWAP:
7892 case ISD::ATOMIC_LOAD_ADD:
7893 case ISD::ATOMIC_LOAD_SUB:
7894 case ISD::ATOMIC_LOAD_AND:
7895 case ISD::ATOMIC_LOAD_OR:
7896 case ISD::ATOMIC_LOAD_XOR:
7897 case ISD::ATOMIC_LOAD_NAND:
7898 case ISD::ATOMIC_LOAD_MIN:
7899 case ISD::ATOMIC_LOAD_MAX:
7900 case ISD::ATOMIC_LOAD_UMIN:
7901 case ISD::ATOMIC_LOAD_UMAX:
7908 if (fence.getOpcode() != ISD::MEMBARRIER)
7912 case ISD::ATOMIC_CMP_SWAP:
7917 case ISD::ATOMIC_SWAP:
7918 case ISD::ATOMIC_LOAD_ADD:
7919 case ISD::ATOMIC_LOAD_SUB:
7920 case ISD::ATOMIC_LOAD_AND:
7921 case ISD::ATOMIC_LOAD_OR:
7922 case ISD::ATOMIC_LOAD_XOR:
7923 case ISD::ATOMIC_LOAD_NAND:
7924 case ISD::ATOMIC_LOAD_MIN:
7925 case ISD::ATOMIC_LOAD_MAX:
7926 case ISD::ATOMIC_LOAD_UMIN:
7927 case ISD::ATOMIC_LOAD_UMAX:
7946 if (N->getOpcode() == ISD::AND) {
7947 if (RHS.getOpcode() == ISD::BITCAST)
7949 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
7974 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
7976 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS);
7978 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf);
8002 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
8003 RHS.getOpcode() == ISD::BUILD_VECTOR) {
8009 if ((LHSOp.getOpcode() != ISD::UNDEF &&
8010 LHSOp.getOpcode() != ISD::Constant &&
8011 LHSOp.getOpcode() != ISD::ConstantFP) ||
8012 (RHSOp.getOpcode() != ISD::UNDEF &&
8013 RHSOp.getOpcode() != ISD::Constant &&
8014 RHSOp.getOpcode() != ISD::ConstantFP))
8018 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
8019 N->getOpcode() == ISD::FDIV) {
8020 if ((RHSOp.getOpcode() == ISD::Constant &&
8022 (RHSOp.getOpcode() == ISD::ConstantFP &&
8035 RHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, RHSOp);
8037 LHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), RVT, LHSOp);
8043 if (FoldOp.getOpcode() != ISD::UNDEF &&
8044 FoldOp.getOpcode() != ISD::Constant &&
8045 FoldOp.getOpcode() != ISD::ConstantFP)
8052 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
8061 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
8072 if (SCC.getOpcode() == ISD::SELECT_CC) {
8073 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(),
8078 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(),
8109 if (LHS.getOpcode() == ISD::LOAD) {
8122 LLD->getExtensionType() != ISD::EXTLOAD &&
8123 RLD->getExtensionType() != ISD::EXTLOAD) ||
8137 if (TheSelect->getOpcode() == ISD::SELECT) {
8142 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(),
8156 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(),
8165 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) {
8173 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ?
8200 ISD::CondCode CC, bool NotExtCompare) {
8227 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
8228 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
8230 return DAG.getNode(ISD::FABS, DL, VT, N0);
8233 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
8234 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
8236 return DAG.getNode(ISD::FABS, DL, VT, N3);
8251 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) !=
8279 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(),
8282 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx,
8294 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
8307 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(),
8312 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
8316 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
8319 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(),
8326 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
8330 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
8340 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND &&
8352 SDValue Shl = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, AndLHS, ShlAmt);
8359 SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt);
8361 return DAG.getNode(ISD::AND, DL, VT, Shr, N3);
8386 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
8390 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
8401 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp,
8412 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) {
8415 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res);
8420 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
8422 TLI.isOperationLegal(ISD::CTLZ, XType))) {
8423 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0);
8424 return DAG.getNode(ISD::SRL, DL, XType, Ctlz,
8429 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
8430 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(),
8433 return DAG.getNode(ISD::SRL, DL, XType,
8434 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0),
8439 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
8440 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0,
8443 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType));
8455 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) ||
8456 (N1C->isAllOnesValue() && CC == ISD::SETGT)) &&
8457 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1))
8459 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) ||
8460 (N1C->isOne() && CC == ISD::SETLT)) &&
8461 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1))
8466 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType,
8470 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(),
8474 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
8483 SDValue N1, ISD::CondCode Cond,
8490 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
8504 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
8527 if (Base.getOpcode() == ISD::ADD) {
8695 case ISD::EntryToken:
8699 case ISD::LOAD:
8700 case ISD::STORE: {
8728 case ISD::TokenFactor:
8767 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
