Lines Matching refs:SEXTLOAD
2618 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
2652 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
4262 // fold (sext (load x)) -> (sext (truncate (sextload x)))
4268 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) {
4275 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
4291 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
4292 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
4298 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) {
4299 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
4315 // (and/or/xor (sextload x), (sext cst))
4320 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()) &&
4330 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, LN0->getDebugLoc(), VT,
4595 if (LN0->getExtensionType() != ISD::SEXTLOAD) {
4816 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
4944 ExtType = ISD::SEXTLOAD;
4983 // If the load was a sextload then the result is a splat of the sign bit
5103 // fold (sext_in_reg (load x)) -> (smaller sextload x)
5104 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
5124 // fold (sext_inreg (extload x)) -> (sextload x)
5129 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
5131 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
5141 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
5146 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
5148 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
