Lines Matching refs:SRL
874 else if (Opc == ISD::SRL)
1115 case ISD::SRL: return visitSRL(N);
1194 case ISD::SRL:
1876 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN,
1879 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL);
1880 AddToWorkList(SRL.getNode());
1930 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
1944 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add);
2088 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2124 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2207 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2237 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2321 // For each of OP in SHL/SRL/SRA/AND...
2325 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
2592 // fold (and (sra)) -> (and (srl)) when possible.
2729 // Recognize (and (shl a, 8), 0xff), (and (srl a, 8), 0xff00)
2732 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
2756 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
2758 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
2771 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8)
2797 // Make sure everything beyond the low halfword is zero since the SRL 16
2807 Res = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Res,
2820 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL)
2843 if (N0.getOpcode() != ISD::SRL)
2865 } else { // Opc == ISD::SRL
2951 DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, BSwap, ShAmt));
3095 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
3106 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
3127 // Match "(X shl/srl V1) & V2" where V2 may not be present.
3144 // Canonicalize shl to left side in a shl/srl pair.
3156 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
3157 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
3195 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
3196 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
3212 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
3213 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
3242 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
3244 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
3256 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
3258 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
3435 BinOpLHSVal->getOpcode() != ISD::SRL) ||
3550 // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or
3551 // (and (srl x, (sub c1, c2), MASK)
3554 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse() &&
3568 Shift = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
3669 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT,
3702 (N0.getOperand(0).getOpcode() == ISD::SRL ||
3727 // If the sign bit is known to be zero, switch this to a SRL.
3729 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1);
3748 // fold (srl c1, c2) -> c1 >>u c2
3750 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C);
3751 // fold (srl 0, x) -> 0
3754 // fold (srl x, c >= size(x)) -> undef
3757 // fold (srl x, 0) -> x
3760 // if (srl x, c) is known to be zero, return 0
3765 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2))
3766 if (N1C && N0.getOpcode() == ISD::SRL &&
3772 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
3776 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2)))
3778 N0.getOperand(0).getOpcode() == ISD::SRL &&
3791 DAG.getNode(ISD::SRL, N0->getDebugLoc(), InnerShiftVT,
3797 // fold (srl (shl x, c), c) -> (and x, cst2)
3806 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
3813 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) {
3815 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT,
3823 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
3827 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1);
3830 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
3837 // zeros, thus the result of the srl will always be zero.
3848 // could be set on input to the CTLZ node. If this bit is set, the SRL
3849 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
3850 // to an SRL/XOR pair, which is likely to simplify more.
3855 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op,
3865 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))).
3875 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
3885 // fold operands of srl based on knowledge that the low bits are not
3896 // Attempt to convert a srl of a load into a narrower zero-extending load.
3905 // %c = srl i32 %b, 1
3915 // However when after the source operand of SRL is optimized into AND, the SRL
4213 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
4495 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
4514 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n)))
4697 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
4743 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
4904 case ISD::SRL:
4917 SRL, V.getDebugLoc(), V.getValueType(),
4946 } else if (Opc == ISD::SRL) {
4947 // Another special-case: SRL is basically zero-extending a narrower value.
4966 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
5104 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
5109 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24)
5110 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible.
5111 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
5112 if (N0.getOpcode() == ISD::SRL) {
5115 // We can turn this into an SRA iff the input to the SRL is already sign
5253 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
5424 X = DAG.getNode(ISD::SRL, X.getDebugLoc(),
6130 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) ||
6133 N1.getOperand(0).getOpcode() == ISD::SRL))) {
6145 // %c = srl i32 %b, 1
6156 // SRL constant is equal to the log2 of the AND constant. The back-end is
6186 // Replace the uses of SRL with SETCC
6815 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal,
8300 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
8307 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(),
8419 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X))))
8424 return DAG.getNode(ISD::SRL, DL, XType, Ctlz,
8428 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1))
8433 return DAG.getNode(ISD::SRL, DL, XType,
8438 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1))
8440 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0,
