Lines Matching refs:EXTLOAD
264 // Only do this if the target has a native EXTLOAD instruction from
266 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
279 DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT,
364 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
479 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
573 // with a "move to register" or "extload into register" instruction, then
971 // that these bits are zero. It is also useful for EXTLOAD, since it
978 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
987 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
1011 assert(!SrcVT.isVector() && "Unsupported extload!");
1024 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1054 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1117 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) && TLI.isTypeLegal(SrcVT)) {
1124 case ISD::EXTLOAD:
1144 assert(ExtType != ISD::EXTLOAD &&
1145 "EXTLOAD should always be supported!");
1146 // Turn the unsupported load into an EXTLOAD followed by an explicit
1148 SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
1358 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr,
1641 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr,
2194 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
2691 // EXTLOAD pair, targeting a temporary location (a stack slot).
