Lines Matching refs:ISD
50 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break;
51 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
52 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
53 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
54 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
55 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
56 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
57 case ISD::CONVERT_RNDSAT:
59 case ISD::CTLZ_ZERO_UNDEF:
60 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
61 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break;
62 case ISD::CTTZ_ZERO_UNDEF:
63 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
64 case ISD::EXTRACT_VECTOR_ELT:
66 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
67 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
68 case ISD::VSELECT: Res = PromoteIntRes_VSELECT(N); break;
69 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
70 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
71 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
72 case ISD::SIGN_EXTEND_INREG:
74 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
75 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
76 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
77 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
78 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
80 case ISD::EXTRACT_SUBVECTOR:
82 case ISD::VECTOR_SHUFFLE:
84 case ISD::INSERT_VECTOR_ELT:
86 case ISD::BUILD_VECTOR:
88 case ISD::SCALAR_TO_VECTOR:
90 case ISD::CONCAT_VECTORS:
93 case ISD::SIGN_EXTEND:
94 case ISD::ZERO_EXTEND:
95 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
97 case ISD::FP_TO_SINT:
98 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
100 case ISD::FP32_TO_FP16:Res = PromoteIntRes_FP32_TO_FP16(N); break;
102 case ISD::AND:
103 case ISD::OR:
104 case ISD::XOR:
105 case ISD::ADD:
106 case ISD::SUB:
107 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
109 case ISD::SDIV:
110 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break;
112 case ISD::UDIV:
113 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break;
115 case ISD::SADDO:
116 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
117 case ISD::UADDO:
118 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
119 case ISD::SMULO:
120 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
122 case ISD::ATOMIC_LOAD:
125 case ISD::ATOMIC_LOAD_ADD:
126 case ISD::ATOMIC_LOAD_SUB:
127 case ISD::ATOMIC_LOAD_AND:
128 case ISD::ATOMIC_LOAD_OR:
129 case ISD::ATOMIC_LOAD_XOR:
130 case ISD::ATOMIC_LOAD_NAND:
131 case ISD::ATOMIC_LOAD_MIN:
132 case ISD::ATOMIC_LOAD_MAX:
133 case ISD::ATOMIC_LOAD_UMIN:
134 case ISD::ATOMIC_LOAD_UMAX:
135 case ISD::ATOMIC_SWAP:
138 case ISD::ATOMIC_CMP_SWAP:
156 return DAG.getNode(ISD::AssertSext, N->getDebugLoc(),
163 return DAG.getNode(ISD::AssertZext, N->getDebugLoc(),
220 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp));
224 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
231 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
245 InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
249 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp);
256 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp));
259 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
270 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
277 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(),
289 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
298 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
299 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
300 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
301 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
317 return DAG.getNode(ISD::SUB, dl, NVT, Op,
325 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), Op.getValueType(), Op);
333 if (N->getOpcode() == ISD::CTTZ) {
339 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, NVT));
347 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, N->getOperand(0),
360 if (N->getOpcode() == ISD::FP_TO_UINT &&
361 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
362 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
363 NewOpc = ISD::FP_TO_SINT;
370 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ?
371 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res,
381 return DAG.getNode(ISD::AssertZext, dl,
398 if (N->getOpcode() == ISD::SIGN_EXTEND)
399 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
401 if (N->getOpcode() == ISD::ZERO_EXTEND)
404 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
414 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
416 ISD::LoadExtType ExtType =
417 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
459 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
464 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
467 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
486 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
498 return DAG.getNode(ISD::VSELECT, N->getDebugLoc(),
505 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(),
530 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
534 return DAG.getNode(ISD::SHL, N->getDebugLoc(),
541 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(),
558 return DAG.getNode(ISD::SRA, N->getDebugLoc(),
567 return DAG.getNode(ISD::SRL, N->getDebugLoc(), NVT, Res, N->getOperand(1));
599 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HalfVT, InOp,
601 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HalfVT, InOp,
603 EOp1 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp1);
604 EOp2 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp2);
606 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2);
610 return DAG.getNode(ISD::TRUNCATE, dl, NVT, Res);
626 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
633 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
653 if (N->getOpcode() == ISD::SMULO) {
660 SDValue Mul = DAG.getNode(ISD::MUL, DL, LHS.getValueType(), LHS, RHS);
665 if (N->getOpcode() == ISD::UMULO) {
667 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul,
670 DAG.getConstant(0, Hi.getValueType()), ISD::SETNE);
673 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(),
675 Overflow = DAG.getSetCC(DL, N->getValueType(1), SExt, Mul, ISD::SETNE);
719 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
721 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
723 Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
726 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
759 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
760 case ISD::ATOMIC_STORE:
763 case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break;
764 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
765 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
766 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
767 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
768 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break;
769 case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break;
770 case ISD::CONVERT_RNDSAT:
772 case ISD::INSERT_VECTOR_ELT:
774 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break;
775 ISD::SCALAR_TO_VECTOR:
777 case ISD::VSELECT:
778 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
779 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
780 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
781 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
782 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
783 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
785 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
786 case ISD::FP16_TO_FP32:
787 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
788 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
790 case ISD::SHL:
791 case ISD::SRA:
792 case ISD::SRL:
793 case ISD::ROTL:
794 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
815 ISD::CondCode CCCode) {
821 case ISD::SETEQ:
822 case ISD::SETNE:
823 case ISD::SETUGE:
824 case ISD::SETUGT:
825 case ISD::SETULE:
826 case ISD::SETULT:
833 case ISD::SETGE:
834 case ISD::SETGT:
835 case ISD::SETLT:
836 case ISD::SETLE:
845 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), Op);
895 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
897 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
923 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
924 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
925 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
926 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) &&
982 EVT SVT = TLI.getSetCCResultType(N->getOpcode() == ISD::SELECT ?
1021 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1022 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(),
1032 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
1049 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), Op);
1060 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1091 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
1092 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
1093 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
1094 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
1096 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break;
1097 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
1098 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
1099 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
1100 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
1102 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
1103 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
1104 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
1105 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
1106 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
1107 case ISD::CTLZ_ZERO_UNDEF:
1108 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
1109 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
1110 case ISD::CTTZ_ZERO_UNDEF:
1111 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
1112 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
1113 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
1114 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
1115 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
1116 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
1117 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
1118 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
1119 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
1120 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
1121 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
1122 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
1123 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
1124 case ISD::ATOMIC_LOAD: ExpandIntRes_ATOMIC_LOAD(N, Lo, Hi); break;
1126 case ISD::ATOMIC_LOAD_ADD:
1127 case ISD::ATOMIC_LOAD_SUB:
1128 case ISD::ATOMIC_LOAD_AND:
1129 case ISD::ATOMIC_LOAD_OR:
1130 case ISD::ATOMIC_LOAD_XOR:
1131 case ISD::ATOMIC_LOAD_NAND:
1132 case ISD::ATOMIC_LOAD_MIN:
1133 case ISD::ATOMIC_LOAD_MAX:
1134 case ISD::ATOMIC_LOAD_UMIN:
1135 case ISD::ATOMIC_LOAD_UMAX:
1136 case ISD::ATOMIC_SWAP: {
1143 case ISD::AND:
1144 case ISD::OR:
1145 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
1147 case ISD::ADD:
1148 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
1150 case ISD::ADDC:
1151 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
1153 case ISD::ADDE:
1154 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
1156 case ISD::SHL:
1157 case ISD::SRA:
1158 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
1160 case ISD::SADDO:
1161 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break;
1162 case ISD::UADDO:
1163 case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break;
1164 case ISD::UMULO:
1165 case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break;
1182 case ISD::ATOMIC_SWAP:
1191 case ISD::ATOMIC_CMP_SWAP:
1200 case ISD::ATOMIC_LOAD_ADD:
1209 case ISD::ATOMIC_LOAD_SUB:
1218 case ISD::ATOMIC_LOAD_AND:
1227 case ISD::ATOMIC_LOAD_OR:
1236 case ISD::ATOMIC_LOAD_XOR:
1245 case ISD::ATOMIC_LOAD_NAND:
1273 if (N->getOpcode() == ISD::SHL) {
1278 Hi = DAG.getNode(ISD::SHL, DL,
1284 TLI.isOperationLegalOrCustom(ISD::ADDC,
1289 Lo = DAG.getNode(ISD::ADDC, DL, VTList, LoOps, 2);
1291 Hi = DAG.getNode(ISD::ADDE, DL, VTList, HiOps, 3);
1293 Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, ShTy));
1294 Hi = DAG.getNode(ISD::OR, DL, NVT,
1295 DAG.getNode(ISD::SHL, DL, NVT, InH,
1297 DAG.getNode(ISD::SRL, DL, NVT, InL,
1303 if (N->getOpcode() == ISD::SRL) {
1308 Lo = DAG.getNode(ISD::SRL, DL,
1315 Lo = DAG.getNode(ISD::OR, DL, NVT,
1316 DAG.getNode(ISD::SRL, DL, NVT, InL,
1318 DAG.getNode(ISD::SHL, DL, NVT, InH,
1320 Hi = DAG.getNode(ISD::SRL, DL, NVT, InH, DAG.getConstant(Amt, ShTy));
1325 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1327 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1330 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1332 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1336 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1339 Lo = DAG.getNode(ISD::OR, DL, NVT,
1340 DAG.getNode(ISD::SRL, DL, NVT, InL,
1342 DAG.getNode(ISD::SHL, DL, NVT, InH,
1344 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, ShTy));
1379 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
1384 case ISD::SHL:
1386 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
1388 case ISD::SRL:
1390 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
1392 case ISD::SRA:
1393 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1395 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1406 SDValue Amt2 = DAG.getNode(ISD::XOR, dl, ShTy, Amt,
1412 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1413 case ISD::SRL:
1414 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1418 if (N->getOpcode() != ISD::SHL)
1428 Hi = DAG.getNode(ISD::OR, dl, NVT, DAG.getNode(Op1, dl, NVT, InH, Amt),Sh2);
1430 if (N->getOpcode() != ISD::SHL)
1455 SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode);
1456 SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
1458 Amt, NVBitsNode, ISD::SETULT);
1463 case ISD::SHL:
1465 LoS = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
1466 HiS = DAG.getNode(ISD::OR, dl, NVT,
1467 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
1470 DAG.getNode(ISD::SRL, dl, NVT, InL, AmtLack));
1474 HiL = DAG.getNode(ISD::SHL, dl, NVT, InL, AmtExcess); // Hi from Lo part.
1476 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL);
1477 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
1479 case ISD::SRL:
1481 HiS = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
1482 LoS = DAG.getNode(ISD::OR, dl, NVT,
1483 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1486 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1490 LoL = DAG.getNode(ISD::SRL, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1492 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL);
1493 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
1495 case ISD::SRA:
1497 HiS = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
1498 LoS = DAG.getNode(ISD::OR, dl, NVT,
1499 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1502 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1505 HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part.
1507 LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1509 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL);
1510 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
1533 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1534 ISD::ADDC : ISD::SUBC,
1539 if (N->getOpcode() == ISD::ADD) {
1540 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1542 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1544 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1546 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1551 if (N->getOpcode() == ISD::ADD) {
1552 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2);
1553 Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2);
1555 ISD::SETULT);
1556 SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1,
1560 ISD::SETULT);
1561 SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2,
1563 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
1565 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2);
1566 Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2);
1569 LoOps[0], LoOps[1], ISD::SETULT);
1570 SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp,
1573 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
1588 if (N->getOpcode() == ISD::ADDC) {
1589 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1591 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1593 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1595 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1636 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
1662 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
1666 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
1668 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1683 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
1687 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
1697 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
1698 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
1718 DAG.getConstant(0, NVT), ISD::SETNE);
1721 SDValue HiLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, NVT, Hi);
1723 Lo = DAG.getNode(ISD::SELECT, dl, NVT, HiNotZero, HiLZ,
1724 DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
1735 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
1736 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
1748 DAG.getConstant(0, NVT), ISD::SETNE);
1750 SDValue LoLZ = DAG.getNode(ISD::CTTZ_ZERO_UNDEF, dl, NVT, Lo);
1753 Lo = DAG.getNode(ISD::SELECT, dl, NVT, LoNotZero, LoLZ,
1754 DAG.getNode(ISD::ADD, dl, NVT, HiLZ,
1781 if (ISD::isNormalLoad(N)) {
1786 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1792 ISD::LoadExtType ExtType = N->getExtensionType();
1810 if (ExtType == ISD::SEXTLOAD) {
1814 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1816 } else if (ExtType == ISD::ZEXTLOAD) {
1820 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1835 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1844 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1861 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1864 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr,
1872 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1877 Lo = DAG.getNode(ISD::OR, dl, NVT, Lo,
1878 DAG.getNode(ISD::SHL, dl, NVT, Hi,
1882 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl,
1910 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT);
1911 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT);
1912 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT);
1913 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT);
1929 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1935 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1936 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1944 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1950 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1951 Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL);
1957 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
1961 ISD::MUL, dl, NVT, LL, RH);
1962 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1963 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1964 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1968 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1969 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1970 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1971 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1972 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1973 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
2002 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
2003 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2021 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
2022 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
2024 Node->getOpcode() == ISD::SADDO ?
2025 ISD::SETEQ : ISD::SETNE);
2027 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
2028 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
2030 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
2073 if (N->getOpcode() == ISD::SHL) {
2074 PartsOpc = ISD::SHL_PARTS;
2075 } else if (N->getOpcode() == ISD::SRL) {
2076 PartsOpc = ISD::SRL_PARTS;
2078 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2079 PartsOpc = ISD::SRA_PARTS;
2102 if (N->getOpcode() == ISD::SHL) {
2112 } else if (N->getOpcode() == ISD::SRL) {
2123 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2152 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
2155 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
2170 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2184 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo,
2189 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
2197 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2227 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
2228 Hi = DAG.getNode(ISD::SRL, dl,
2231 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
2242 SDValue Sum = DAG.getNode(N->getOpcode() == ISD::UADDO ?
2243 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2250 N->getOpcode () == ISD::UADDO ?
2251 ISD::SETULT : ISD::SETUGT);
2266 if (N->getOpcode() == ISD::UMULO) {
2270 SDValue MUL = DAG.getNode(ISD::MUL, DL, LHS.getValueType(), LHS, RHS);
2276 RHS, DAG.getConstant(0, VT), ISD::SETNE);
2277 SDValue NotZero = DAG.getNode(ISD::SELECT, dl, VT, isZero,
2279 SDValue DIV = DAG.getNode(ISD::UDIV, DL, LHS.getValueType(), MUL, NotZero);
2281 Overflow = DAG.getSetCC(DL, N->getValueType(1), DIV, LHS, ISD::SETNE);
2334 ISD::SETNE);
2386 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0));
2412 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
2445 case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break;
2446 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
2447 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
2448 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
2449 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
2450 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
2451 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
2452 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
2453 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
2454 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break;
2455 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
2456 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
2458 case ISD::SHL:
2459 case ISD::SRA:
2460 case ISD::SRL:
2461 case ISD::ROTL:
2462 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
2463 case ISD::RETURNADDR:
2464 case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
2466 case ISD::ATOMIC_STORE: Res = ExpandIntOp_ATOMIC_STORE(N); break;
2488 ISD::CondCode &CCCode,
2494 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
2499 NewLHS = DAG.getNode(ISD::AND, dl,
2507 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
2508 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
2509 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS);
2517 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
2518 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
2525 ISD::CondCode LowCC;
2528 case ISD::SETLT:
2529 case ISD::SETULT: LowCC = ISD::SETULT; break;
2530 case ISD::SETGT:
2531 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
2532 case ISD::SETLE:
2533 case ISD::SETULE: LowCC = ISD::SETULE; break;
2534 case ISD::SETGE:
2535 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
2554 Tmp2 = DAG.getNode(ISD::SETCC, dl,
2562 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
2563 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
2565 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
2566 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
2576 LHSHi, RHSHi, ISD::SETEQ, false,
2580 LHSHi, RHSHi, ISD::SETEQ);
2581 NewLHS = DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(),
2588 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
2595 CCCode = ISD::SETNE;
2606 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
2613 CCCode = ISD::SETNE;
2624 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
2667 if (ISD::isNormalStore(N))
2670 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2705 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2711 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2727 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
2730 Hi = DAG.getNode(ISD::OR, dl, NVT, Hi,
2731 DAG.getNode(ISD::SRL, dl, NVT, Lo,
2741 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2749 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2756 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), InL);
2781 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
2783 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op);
2810 ISD::SETLT);
2821 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
2824 FudgePtr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), FudgePtr, Offset);
2829 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(),
2834 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
2846 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
2875 SDValue Index = DAG.getNode(ISD::ADD, dl, BaseIdx.getValueType(),
2877 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2880 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, Ext);
2885 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, &Ops[0], Ops.size());
2920 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(i));
2924 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, &Ops[0], Ops.size());
2939 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(0));
2941 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NOutVT, Op);
2965 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2967 Ops[i * NumElem + j] = DAG.getNode(ISD::ANY_EXTEND, dl, OutElemTy, Ext);
2971 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, &Ops[0], Ops.size());
2984 SDValue ConvElem = DAG.getNode(ISD::ANY_EXTEND, dl,
2986 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NOutVT,
2994 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3020 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SclrTy,
3022 SDValue Tr = DAG.getNode(ISD::TRUNCATE, dl, RetSclrTy, Ex);
3027 return DAG.getNode(ISD::BUILD_VECTOR, dl, N->getValueType(0),
