Lines Matching refs:ISD
15 // ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition
16 // on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the
18 // expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC;
22 // This does not legalize vector manipulations like ISD::BUILD_VECTOR,
129 if (Op.getOpcode() == ISD::LOAD) {
131 ISD::LoadExtType ExtType = LD->getExtensionType();
132 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD) {
138 } else if (Op.getOpcode() == ISD::STORE) {
168 case ISD::ADD:
169 case ISD::SUB:
170 case ISD::MUL:
171 case ISD::SDIV:
172 case ISD::UDIV:
173 case ISD::SREM:
174 case ISD::UREM:
175 case ISD::FADD:
176 case ISD::FSUB:
177 case ISD::FMUL:
178 case ISD::FDIV:
179 case ISD::FREM:
180 case ISD::AND:
181 case ISD::OR:
182 case ISD::XOR:
183 case ISD::SHL:
184 case ISD::SRA:
185 case ISD::SRL:
186 case ISD::ROTL:
187 case ISD::ROTR:
188 case ISD::CTLZ:
189 case ISD::CTTZ:
190 case ISD::CTLZ_ZERO_UNDEF:
191 case ISD::CTTZ_ZERO_UNDEF:
192 case ISD::CTPOP:
193 case ISD::SELECT:
194 case ISD::VSELECT:
195 case ISD::SELECT_CC:
196 case ISD::SETCC:
197 case ISD::ZERO_EXTEND:
198 case ISD::ANY_EXTEND:
199 case ISD::TRUNCATE:
200 case ISD::SIGN_EXTEND:
201 case ISD::FP_TO_SINT:
202 case ISD::FP_TO_UINT:
203 case ISD::FNEG:
204 case ISD::FABS:
205 case ISD::FSQRT:
206 case ISD::FSIN:
207 case ISD::FCOS:
208 case ISD::FPOWI:
209 case ISD::FPOW:
210 case ISD::FLOG:
211 case ISD::FLOG2:
212 case ISD::FLOG10:
213 case ISD::FEXP:
214 case ISD::FEXP2:
215 case ISD::FCEIL:
216 case ISD::FTRUNC:
217 case ISD::FRINT:
218 case ISD::FNEARBYINT:
219 case ISD::FFLOOR:
220 case ISD::SIGN_EXTEND_INREG:
223 case ISD::FP_ROUND_INREG:
226 case ISD::SINT_TO_FP:
227 case ISD::UINT_TO_FP:
248 if (Node->getOpcode() == ISD::VSELECT)
250 else if (Node->getOpcode() == ISD::UINT_TO_FP)
252 else if (Node->getOpcode() == ISD::FNEG)
254 else if (Node->getOpcode() == ISD::SETCC)
275 // in a different type. For example, x86 promotes ISD::AND on v2i32 to
286 Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Op.getOperand(j));
293 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
303 ISD::LoadExtType ExtType = LD->getExtensionType();
318 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
325 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
327 SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl,
368 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
376 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
381 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
401 if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
402 TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
403 TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand)
411 Op1 = DAG.getNode(ISD::BITCAST, DL, VT, Op1);
412 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2);
416 SDValue NotMask = DAG.getNode(ISD::XOR, DL, VT, Mask, AllOnes);
418 Op1 = DAG.getNode(ISD::AND, DL, VT, Op1, Mask);
419 Op2 = DAG.getNode(ISD::AND, DL, VT, Op2, NotMask);
420 SDValue Val = DAG.getNode(ISD::OR, DL, VT, Op1, Op2);
421 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
429 if (TLI.getOperationAction(ISD::SINT_TO_FP, VT) == TargetLowering::Expand ||
430 TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand)
450 SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Op.getOperand(0), HalfWord);
451 SDValue LO = DAG.getNode(ISD::AND, DL, VT, Op.getOperand(0), HalfWordMask);
455 SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), HI);
456 ISD::FMUL, DL, Op.getValueType(), fHI, TWOHW);
457 SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), LO);
460 return DAG.getNode(ISD::FADD, DL, Op.getValueType(), fHI, fLO);
465 if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) {
467 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
482 SDValue LHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, LHS,
484 SDValue RHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, RHS,
486 Ops[i] = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(TmpEltVT),
488 Ops[i] = DAG.getNode(ISD::SELECT, dl, EltVT, Ops[i],
493 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElems);
