Lines Matching refs:ISD
49 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break;
50 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break;
51 case ISD::BUILD_VECTOR: R = N->getOperand(0); break;
52 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break;
53 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
54 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break;
55 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break;
56 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
57 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
58 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
59 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
60 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;
61 case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break;
62 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
63 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
64 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
65 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
66 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
67 case ISD::ANY_EXTEND:
68 case ISD::CTLZ:
69 case ISD::CTPOP:
70 case ISD::CTTZ:
71 case ISD::FABS:
72 case ISD::FCEIL:
73 case ISD::FCOS:
74 case ISD::FEXP:
75 case ISD::FEXP2:
76 case ISD::FFLOOR:
77 case ISD::FLOG:
78 case ISD::FLOG10:
79 case ISD::FLOG2:
80 case ISD::FNEARBYINT:
81 case ISD::FNEG:
82 case ISD::FP_EXTEND:
83 case ISD::FP_TO_SINT:
84 case ISD::FP_TO_UINT:
85 case ISD::FRINT:
86 case ISD::FSIN:
87 case ISD::FSQRT:
88 case ISD::FTRUNC:
89 case ISD::SIGN_EXTEND:
90 case ISD::SINT_TO_FP:
91 case ISD::TRUNCATE:
92 case ISD::UINT_TO_FP:
93 case ISD::ZERO_EXTEND:
97 case ISD::ADD:
98 case ISD::AND:
99 case ISD::FADD:
100 case ISD::FDIV:
101 case ISD::FMUL:
102 case ISD::FPOW:
103 case ISD::FREM:
104 case ISD::FSUB:
105 case ISD::MUL:
106 case ISD::OR:
107 case ISD::SDIV:
108 case ISD::SREM:
109 case ISD::SUB:
110 case ISD::UDIV:
111 case ISD::UREM:
112 case ISD::XOR:
113 case ISD::SHL:
114 case ISD::SRA:
115 case ISD::SRL:
140 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
156 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(),
164 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(),
170 return DAG.getNode(ISD::FPOWI, N->getDebugLoc(),
181 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, Op);
188 SDValue Result = DAG.getLoad(ISD::UNINDEXED,
226 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, InOp);
244 Cond = DAG.getNode(ISD::AND, N->getDebugLoc(), CondVT,
251 Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), CondVT,
256 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
263 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
270 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), LHS.getValueType(),
288 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
298 if (Arg.getOpcode() == ISD::UNDEF)
315 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
319 ISD::NodeType ExtendCode =
344 case ISD::BITCAST:
347 case ISD::CONCAT_VECTORS:
350 case ISD::EXTRACT_VECTOR_ELT:
353 case ISD::STORE:
378 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
388 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), N->getValueType(0),
398 Res = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0),
453 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
454 case ISD::VSELECT:
455 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
456 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
457 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
458 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break;
459 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
460 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
461 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
462 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
463 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
464 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
465 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
466 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
467 case ISD::LOAD:
470 case ISD::SETCC:
473 case ISD::VECTOR_SHUFFLE:
477 case ISD::ANY_EXTEND:
478 case ISD::CONVERT_RNDSAT:
479 case ISD::CTLZ:
480 case ISD::CTTZ:
481 case ISD::CTLZ_ZERO_UNDEF:
482 case ISD::CTTZ_ZERO_UNDEF:
483 case ISD::CTPOP:
484 case ISD::FABS:
485 case ISD::FCEIL:
486 case ISD::FCOS:
487 case ISD::FEXP:
488 case ISD::FEXP2:
489 case ISD::FFLOOR:
490 case ISD::FLOG:
491 case ISD::FLOG10:
492 case ISD::FLOG2:
493 case ISD::FNEARBYINT:
494 case ISD::FNEG:
495 case ISD::FP_EXTEND:
496 case ISD::FP_ROUND:
497 case ISD::FP_TO_SINT:
498 case ISD::FP_TO_UINT:
499 case ISD::FRINT:
500 case ISD::FSIN:
501 case ISD::FSQRT:
502 case ISD::FTRUNC:
503 case ISD::SIGN_EXTEND:
504 case ISD::SINT_TO_FP:
505 case ISD::TRUNCATE:
506 case ISD::UINT_TO_FP:
507 case ISD::ZERO_EXTEND:
511 case ISD::ADD:
512 case ISD::SUB:
513 case ISD::MUL:
514 case ISD::FADD:
515 case ISD::FSUB:
516 case ISD::FMUL:
517 case ISD::SDIV:
518 case ISD::UDIV:
519 case ISD::FDIV:
520 case ISD::FPOW:
521 case ISD::AND:
522 case ISD::OR:
523 case ISD::XOR:
524 case ISD::SHL:
525 case ISD::SRA:
526 case ISD::SRL:
527 case ISD::UREM:
528 case ISD::SREM:
529 case ISD::FREM:
579 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
580 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
588 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
589 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
603 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
604 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
614 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, &LoOps[0], LoOps.size());
617 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, &HiOps[0], HiOps.size());
635 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, &LoOps[0], LoOps.size());
638 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, &HiOps[0], HiOps.size());
650 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx);
652 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec,
660 Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1));
661 Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1));
691 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
694 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt,
721 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
734 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));
740 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
745 ISD::LoadExtType ExtType = LD->getExtensionType();
758 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset,
763 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
765 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset,
771 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
793 LL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0),
795 LH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0),
798 RL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1),
800 RH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1),
822 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
824 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
828 if (N->getOpcode() == ISD::FP_ROUND) {
831 } else if (N->getOpcode() == ISD::CONVERT_RNDSAT) {
838 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
935 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
940 Output = DAG.getNode(ISD::BUILD_VECTOR,dl,NewVT, &SVOps[0], SVOps.size());
981 case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break;
982 case ISD::BITCAST: Res = SplitVecOp_BITCAST(N); break;
983 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
984 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
985 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break;
986 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break;
987 case ISD::STORE:
991 case ISD::CTTZ:
992 case ISD::CTLZ:
993 case ISD::CTPOP:
994 case ISD::FP_EXTEND:
995 case ISD::FP_TO_SINT:
996 case ISD::FP_TO_UINT:
997 case ISD::SINT_TO_FP:
998 case ISD::UINT_TO_FP:
999 case ISD::FTRUNC:
1000 case ISD::TRUNCATE:
1001 case ISD::SIGN_EXTEND:
1002 case ISD::ZERO_EXTEND:
1003 case ISD::ANY_EXTEND:
1038 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
1053 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), N->getValueType(0),
1071 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx);
1073 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi,
1108 return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr,
1140 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1152 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1169 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT,
1175 return DAG.getNode(ISD::BUILD_VECTOR, DL, N->getValueType(0),
1192 LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2));
1193 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2));
1194 SDValue Con = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideResVT, LoRes, HiRes);
1210 Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1));
1211 Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1));
1213 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
1241 case ISD::MERGE_VALUES: Res = WidenVecRes_MERGE_VALUES(N, ResNo); break;
1242 case ISD::BITCAST: Res = WidenVecRes_BITCAST(N); break;
1243 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break;
1244 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break;
1245 case ISD::CONVERT_RNDSAT: Res = WidenVecRes_CONVERT_RNDSAT(N); break;
1246 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break;
1247 case ISD::FP_ROUND_INREG: Res = WidenVecRes_InregOp(N); break;
1248 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;
1249 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break;
1250 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break;
1251 case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break;
1252 case ISD::VSELECT:
1253 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
1254 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
1255 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break;
1256 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
1257 case ISD::VECTOR_SHUFFLE:
1260 case ISD::ADD:
1261 case ISD::AND:
1262 case ISD::BSWAP:
1263 case ISD::FADD:
1264 case ISD::FCOPYSIGN:
1265 case ISD::FDIV:
1266 case ISD::FMUL:
1267 case ISD::FPOW:
1268 case ISD::FREM:
1269 case ISD::FSUB:
1270 case ISD::MUL:
1271 ISD::MULHS:
1272 case ISD::MULHU:
1273 case ISD::OR:
1274 case ISD::SDIV:
1275 case ISD::SREM:
1276 case ISD::UDIV:
1277 case ISD::UREM:
1278 case ISD::SUB:
1279 case ISD::XOR:
1283 case ISD::FPOWI:
1287 case ISD::SHL:
1288 case ISD::SRA:
1289 case ISD::SRL:
1293 case ISD::ANY_EXTEND:
1294 case ISD::FP_EXTEND:
1295 case ISD::FP_ROUND:
1296 case ISD::FP_TO_SINT:
1297 case ISD::FP_TO_UINT:
1298 case ISD::SIGN_EXTEND:
1299 case ISD::SINT_TO_FP:
1300 case ISD::TRUNCATE:
1301 case ISD::UINT_TO_FP:
1302 case ISD::ZERO_EXTEND:
1306 case ISD::CTLZ:
1307 case ISD::CTPOP:
1308 case ISD::CTTZ:
1309 case ISD::FABS:
1310 case ISD::FCEIL:
1311 case ISD::FCOS:
1312 case ISD::FEXP:
1313 case ISD::FEXP2:
1314 case ISD::FFLOOR:
1315 case ISD::FLOG:
1316 case ISD::FLOG10:
1317 case ISD::FLOG2:
1318 case ISD::FNEARBYINT:
1319 case ISD::FNEG:
1320 case ISD::FRINT:
1321 case ISD::FSIN:
1322 case ISD::FSQRT:
1323 case ISD::FTRUNC:
1374 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1,
1376 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2,
1389 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT,
1391 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT,
1429 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp,
1446 ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl,
1467 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &ConcatOps[0], NumOps);
1509 SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT,
1517 SDValue InVal = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InWidenVT,
1532 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, InEltVT, InOp,
1544 return DAG.getNode(ISD::BUILD_VECTOR, DL, WidenVT, &Ops[0], WidenNumElts);
1618 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
1633 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
1668 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl,
1671 NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl,
1673 return DAG.getNode(ISD::BITCAST, dl, WidenVT, NewVec);
1695 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &NewOps[0], NewOps.size());
1718 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &Ops[0], NumConcat);
1726 if (N->getOperand(i).getOpcode() != ISD::UNDEF)
1758 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
1764 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1782 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
1809 InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, &Ops[0],NumConcat);
1816 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp,
1832 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
1842 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1866 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx);
1875 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
1881 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1886 return DAG.getNode(ISD::INSERT_VECTOR_ELT, N->getDebugLoc(),
1893 ISD::LoadExtType ExtType = LD->getExtensionType();
1897 if (ExtType != ISD::NON_EXTLOAD)
1909 NewChain = DAG.getNode(ISD::TokenFactor, LD->getDebugLoc(), MVT::Other,
1921 return DAG.getNode(ISD::SCALAR_TO_VECTOR, N->getDebugLoc(),
1952 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(),
1966 return DAG.getNode(ISD::SETCC, N->getDebugLoc(), WidenVT,
2021 return DAG.getNode(ISD::SETCC, N->getDebugLoc(),
2044 case ISD::BITCAST: Res = WidenVecOp_BITCAST(N); break;
2045 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break;
2046 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break;
2047 case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break;
2048 case ISD::STORE: Res = WidenVecOp_STORE(N); break;
2049 case ISD::SETCC: Res = WidenVecOp_SETCC(N); break;
2051 case ISD::FP_EXTEND:
2052 case ISD::FP_TO_SINT:
2053 case ISD::FP_TO_UINT:
2054 case ISD::SINT_TO_FP:
2055 case ISD::UINT_TO_FP:
2056 case ISD::TRUNCATE:
2057 case ISD::SIGN_EXTEND:
2058 case ISD::ZERO_EXTEND:
2059 case ISD::ANY_EXTEND:
2098 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
2101 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts);
2118 SDValue BitOp = DAG.getNode(ISD::BITCAST, dl, NewVT, InOp);
2119 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp,
2147 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2150 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts);
2155 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(),
2161 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(),
2179 return DAG.getNode(ISD::TokenFactor, ST->getDebugLoc(),
2195 SDValue WideSETCC = DAG.getNode(ISD::SETCC, N->getDebugLoc(),
2202 SDValue CC = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl,
2283 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT,LdOps[Start]);
2290 VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, VecOp);
2295 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i],
2298 return DAG.getNode(ISD::BITCAST, dl, VecTy, VecOp);
2338 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp);
2339 return DAG.getNode(ISD::BITCAST, dl, WidenVT, VecOp);
2351 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &ConcatOps[0],
2365 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2387 L = DAG.getNode(ISD::CONCAT_VECTORS, dl, LdOp->getValueType(0),
2430 ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy,
2439 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
2453 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &WidenOps[0],NumOps);
2459 ISD::LoadExtType ExtType) {
2488 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
2501 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], Ops.size());
2536 SDValue EOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp,
2545 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2552 SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp);
2556 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp,
2564 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2601 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
2608 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
2610 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
2643 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, &Ops[0], NumConcat);
2647 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp,
2656 Ops[Idx] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2662 return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &Ops[0], WidenNumElts);
