Lines Matching refs:ISD
106 // ISD Namespace
111 bool ISD::isBuildVectorAllOnes(const SDNode *N) {
113 if (N->getOpcode() == ISD::BITCAST)
116 if (N->getOpcode() != ISD::BUILD_VECTOR) return false;
121 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF)
153 N->getOperand(i).getOpcode() != ISD::UNDEF)
161 bool ISD::isBuildVectorAllZeros(const SDNode *N) {
163 if (N->getOpcode() == ISD::BITCAST)
166 if (N->getOpcode() != ISD::BUILD_VECTOR) return false;
171 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF)
193 N->getOperand(i).getOpcode() != ISD::UNDEF)
199 /// ISD::SCALAR_TO_VECTOR node or a BUILD_VECTOR node where only the low
201 bool ISD::isScalarToVector(const SDNode *N) {
202 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR)
205 if (N->getOpcode() != ISD::BUILD_VECTOR)
207 if (N->getOperand(0).getOpcode() == ISD::UNDEF)
214 if (V.getOpcode() != ISD::UNDEF)
222 ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) {
227 return ISD::CondCode((Operation & ~6) | // Keep the N, U, E bits
234 ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) {
241 if (Operation > ISD::SETTRUE2)
244 return ISD::CondCode(Operation);
251 static int isSignedOp(ISD::CondCode Opcode) {
254 case ISD::SETEQ:
255 case ISD::SETNE: return 0;
256 case ISD::SETLT:
257 case ISD::SETLE:
258 case ISD::SETGT:
259 case ISD::SETGE: return 1;
260 case ISD::SETULT:
261 case ISD::SETULE:
262 case ISD::SETUGT:
263 case ISD::SETUGE: return 2;
271 ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2,
275 return ISD::SETCC_INVALID;
281 if (Op > ISD::SETTRUE2)
285 if (isInteger && Op == ISD::SETUNE) // e.g. SETUGT | SETULT
286 Op = ISD::SETNE;
288 return ISD::CondCode(Op);
295 ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2,
299 return ISD::SETCC_INVALID;
302 ISD::CondCode Result = ISD::CondCode(Op1 & Op2);
308 case ISD::SETUO : Result = ISD::SETFALSE; break; // SETUGT & SETULT
309 case ISD::SETOEQ: // SETEQ & SETU[LG]E
310 case ISD::SETUEQ: Result = ISD::SETEQ ; break; // SETUGE & SETULE
311 case ISD::SETOLT: Result = ISD::SETULT ; break; // SETULT & SETNE
312 case ISD::SETOGT: Result = ISD::SETUGT ; break; // SETUGT & SETNE
367 case ISD::TargetExternalSymbol:
368 case ISD::ExternalSymbol:
371 case ISD::TargetConstant:
372 case ISD::Constant:
375 case ISD::TargetConstantFP:
376 case ISD::ConstantFP: {
380 case ISD::TargetGlobalAddress:
381 case ISD::GlobalAddress:
382 case ISD::TargetGlobalTLSAddress:
383 case ISD::GlobalTLSAddress: {
390 case ISD::BasicBlock:
393 case ISD::Register:
396 case ISD::RegisterMask:
399 case ISD::SRCVALUE:
402 case ISD::FrameIndex:
403 case ISD::TargetFrameIndex:
406 case ISD::JumpTable:
407 case ISD::TargetJumpTable:
411 case ISD::ConstantPool:
412 case ISD::TargetConstantPool: {
423 case ISD::LOAD: {
429 case ISD::STORE: {
435 case ISD::ATOMIC_CMP_SWAP:
436 case ISD::ATOMIC_SWAP:
437 case ISD::ATOMIC_LOAD_ADD:
438 case ISD::ATOMIC_LOAD_SUB:
439 case ISD::ATOMIC_LOAD_AND:
440 case ISD::ATOMIC_LOAD_OR:
441 case ISD::ATOMIC_LOAD_XOR:
442 case ISD::ATOMIC_LOAD_NAND:
443 case ISD::ATOMIC_LOAD_MIN:
444 case ISD::ATOMIC_LOAD_MAX:
445 case ISD::ATOMIC_LOAD_UMIN:
446 case ISD::ATOMIC_LOAD_UMAX:
447 case ISD::ATOMIC_LOAD:
448 case ISD::ATOMIC_STORE: {
454 case ISD::VECTOR_SHUFFLE: {
461 case ISD::TargetBlockAddress:
462 case ISD::BlockAddress: {
488 encodeMemSDNodeFlags(int ConvType, ISD::MemIndexedMode AM, bool isVolatile,
512 case ISD::HANDLENODE:
513 case ISD::EH_LABEL:
613 N->NodeType = ISD::DELETED_NODE;
633 case ISD::HANDLENODE: return false; // noop.
634 case ISD::CONDCODE:
640 case ISD::ExternalSymbol:
643 case ISD::TargetExternalSymbol: {
650 case ISD::VALUETYPE: {
662 assert(N->getOpcode() != ISD::DELETED_NODE && "DELETED_NODE in CSEMap!");
663 assert(N->getOpcode() != ISD::EntryToken && "EntryToken in CSEMap!");
772 case ISD::BUILD_PAIR: {
786 case ISD::BUILD_VECTOR: {
857 OptLevel(OL), EntryNode(ISD::EntryToken, DebugLoc(), getVTList(MVT::Other)),
904 getNode(ISD::ANY_EXTEND, DL, VT, Op) :
905 getNode(ISD::TRUNCATE, DL, VT, Op);
910 getNode(ISD::SIGN_EXTEND, DL, VT, Op) :
911 getNode(ISD::TRUNCATE, DL, VT, Op);
916 ISD::ZERO_EXTEND, DL, VT, Op) :
917 getNode(ISD::TRUNCATE, DL, VT, Op);
928 return getNode(ISD::AND, DL, Op.getValueType(), Op,
938 return getNode(ISD::XOR, DL, VT, Val, NegOne);
972 unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant;
992 Result = getNode(ISD::BUILD_VECTOR, DebugLoc(), VT, &Ops[0], Ops.size());
1014 unsigned Opc = isTarget ? ISD::TargetConstantFP : ISD::ConstantFP;
1035 Result = getNode(ISD::BUILD_VECTOR, DebugLoc(), VT, &Ops[0], Ops.size());
1078 Opc = isTargetGA ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress;
1080 Opc = isTargetGA ? ISD::TargetGlobalAddress : ISD::GlobalAddress;
1099 unsigned Opc = isTarget ? ISD::TargetFrameIndex : ISD::FrameIndex;
1117 unsigned Opc = isTarget ? ISD::TargetJumpTable : ISD::JumpTable;
1141 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool;
1168 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool;
1188 AddNodeIDNode(ID, ISD::BasicBlock, getVTList(MVT::Other), 0, 0);
1233 SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) {
1269 if (N1.getOpcode() == ISD::UNDEF && N2.getOpcode() == ISD::UNDEF)
1289 if (N1.getOpcode() == ISD::UNDEF)
1295 bool N2Undef = N2.getOpcode() == ISD::UNDEF;
1329 AddNodeIDNode(ID, ISD::VECTOR_SHUFFLE, getVTList(VT), Ops, 2);
1353 ISD::CvtCode Code) {
1357 (Code == ISD::CVT_UU || Code == ISD::CVT_SS || Code == ISD::CVT_FF))
1362 AddNodeIDNode(ID, ISD::CONVERT_RNDSAT, getVTList(VT), &Ops[0], 5);
1376 AddNodeIDNode(ID, ISD::Register, getVTList(VT), 0, 0);
1390 AddNodeIDNode(ID, ISD::RegisterMask, getVTList(MVT::Untyped), 0, 0);
1405 AddNodeIDNode(ID, ISD::EH_LABEL, getVTList(MVT::Other), &Ops[0], 1);
1421 unsigned Opc = isTarget ? ISD::TargetBlockAddress : ISD::BlockAddress;
1442 AddNodeIDNode(ID, ISD::SRCVALUE, getVTList(MVT::Other), 0, 0);
1458 AddNodeIDNode(ID, ISD::MDNODE_SDNODE, getVTList(MVT::Other), 0, 0);
1479 ISD::NodeType Opcode = OpTy.bitsGT(ShTy) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
1513 SDValue N2, ISD::CondCode Cond, DebugLoc dl) {
1517 case ISD::SETFALSE:
1518 case ISD::SETFALSE2: return getConstant(0, VT);
1519 case ISD::SETTRUE:
1520 case ISD::SETTRUE2: return getConstant(1, VT);
1522 case ISD::SETOEQ:
1523 case ISD::SETOGT:
1524 case ISD::SETOGE:
1525 case ISD::SETOLT:
1526 case ISD::SETOLE:
1527 case ISD::SETONE:
1528 case ISD::SETO:
1529 case ISD::SETUO:
1530 case ISD::SETUEQ:
1531 case ISD::SETUNE:
1543 case ISD::SETEQ: return getConstant(C1 == C2, VT);
1544 case ISD::SETNE: return getConstant(C1 != C2, VT);
1545 case ISD::SETULT: return getConstant(C1.ult(C2), VT);
1546 case ISD::SETUGT: return getConstant(C1.ugt(C2), VT);
1547 case ISD::SETULE: return getConstant(C1.ule(C2), VT);
1548 case ISD::SETUGE: return getConstant(C1.uge(C2), VT);
1549 case ISD::SETLT: return getConstant(C1.slt(C2), VT);
1550 case ISD::SETGT: return getConstant(C1.sgt(C2), VT);
1551 case ISD::SETLE: return getConstant(C1.sle(C2), VT);
1552 case ISD::SETGE: return getConstant(C1.sge(C2), VT);
1565 case ISD::SETEQ: if (R==APFloat::cmpUnordered)
1568 case ISD::SETOEQ: return getConstant(R==APFloat::cmpEqual, VT);
1569 case ISD::SETNE: if (R==APFloat::cmpUnordered)
1572 case ISD::SETONE: return getConstant(R==APFloat::cmpGreaterThan ||
1574 case ISD::SETLT: if (R==APFloat::cmpUnordered)
1577 case ISD::SETOLT: return getConstant(R==APFloat::cmpLessThan, VT);
1578 case ISD::SETGT: if (R==APFloat::cmpUnordered)
1581 case ISD::SETOGT: return getConstant(R==APFloat::cmpGreaterThan, VT);
1582 case ISD::SETLE: if (R==APFloat::cmpUnordered)
1585 case ISD::SETOLE: return getConstant(R==APFloat::cmpLessThan ||
1587 case ISD::SETGE: if (R==APFloat::cmpUnordered)
1590 case ISD::SETOGE: return getConstant(R==APFloat::cmpGreaterThan ||
1592 case ISD::SETO: return getConstant(R!=APFloat::cmpUnordered, VT);
1593 case ISD::SETUO: return getConstant(R==APFloat::cmpUnordered, VT);
1594 case ISD::SETUEQ: return getConstant(R==APFloat::cmpUnordered ||
1596 case ISD::SETUNE: return getConstant(R!=APFloat::cmpEqual, VT);
1597 case ISD::SETULT: return getConstant(R==APFloat::cmpUnordered ||
1599 case ISD::SETUGT: return getConstant(R==APFloat::cmpGreaterThan ||
1601 case ISD::SETULE: return getConstant(R!=APFloat::cmpGreaterThan, VT);
1602 case ISD::SETUGE: return getConstant(R!=APFloat::cmpLessThan, VT);
1606 return getSetCC(dl, VT, N2, N1, ISD::getSetCCSwappedOperands(Cond));
1651 case ISD::Constant:
1656 case ISD::AND:
1668 case ISD::OR:
1679 case ISD::XOR: {
1692 case ISD::MUL: {
1715 case ISD::UDIV: {
1733 case ISD::SELECT:
1743 case ISD::SELECT_CC:
1753 case ISD::SADDO:
1754 case ISD::UADDO:
1755 case ISD::SSUBO:
1756 case ISD::USUBO:
1757 case ISD::SMULO:
1758 case ISD::UMULO:
1762 case ISD::SETCC:
1768 case ISD::SHL:
1785 case ISD::SRL:
1803 case ISD::SRA:
1831 case ISD::SIGN_EXTEND_INREG: {
1867 case ISD::CTTZ:
1868 case ISD::CTTZ_ZERO_UNDEF:
1869 case ISD::CTLZ:
1870 case ISD::CTLZ_ZERO_UNDEF:
1871 case ISD::CTPOP: {
1877 case ISD::LOAD: {
1879 if (ISD::isZEXTLoad(Op.getNode())) {
1888 case ISD::ZERO_EXTEND: {
1900 case ISD::SIGN_EXTEND: {
1926 case ISD::ANY_EXTEND: {
1936 case ISD::TRUNCATE: {
1947 case ISD::AssertZext: {
1954 case ISD::FGETSIGN:
1959 case ISD::SUB: {
1982 case ISD::ADD:
1983 case ISD::ADDE: {
1996 if (Op.getOpcode() == ISD::ADD) {
2009 case ISD::SREM:
2034 case ISD::UREM: {
2057 case ISD::FrameIndex:
2058 case ISD::TargetFrameIndex:
2067 if (Op.getOpcode() < ISD::BUILTIN_OP_END)
2070 case ISD::INTRINSIC_WO_CHAIN:
2071 case ISD::INTRINSIC_W_CHAIN:
2072 case ISD::INTRINSIC_VOID:
2096 case ISD::AssertSext:
2099 case ISD::AssertZext:
2103 case ISD::Constant: {
2108 case ISD::SIGN_EXTEND:
2112 case ISD::SIGN_EXTEND_INREG:
2121 case ISD::SRA:
2129 case ISD::SHL:
2138 case ISD::AND:
2139 case ISD::OR:
2140 case ISD::XOR: // NOT is handled here.
2152 case ISD::SELECT:
2158 case ISD::SADDO:
2159 case ISD::UADDO:
2160 case ISD::SSUBO:
2161 case ISD::USUBO:
2162 case ISD::SMULO:
2163 case ISD::UMULO:
2167 case ISD::SETCC:
2173 case ISD::ROTL:
2174 case ISD::ROTR:
2179 if (Op.getOpcode() == ISD::ROTR)
2188 case ISD::ADD:
2215 case ISD::SUB:
2242 case ISD::TRUNCATE:
2249 if (Op.getOpcode() == ISD::LOAD) {
2254 case ISD::SEXTLOAD: // '17' bits known
2257 case ISD::ZEXTLOAD: // '16' bits known
2264 if (Op.getOpcode() >= ISD::BUILTIN_OP_END ||
2265 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
2266 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
2267 Op.getOpcode() == ISD::INTRINSIC_VOID) {
2297 /// ISD::ADD with a ConstantSDNode on the right-hand side, or if it is an
2298 /// ISD::OR with a ConstantSDNode that is guaranteed to have the same
2302 if ((Op.getOpcode() != ISD::ADD && Op.getOpcode() != ISD::OR) ||
2306 if (Op.getOpcode() == ISD::OR &&
2337 case ISD::OR:
2385 case ISD::SIGN_EXTEND:
2387 case ISD::ANY_EXTEND:
2388 case ISD::ZERO_EXTEND:
2389 case ISD::TRUNCATE:
2391 case ISD::UINT_TO_FP:
2392 case ISD::SINT_TO_FP: {
2397 Opcode==ISD::SINT_TO_FP,
2401 case ISD::BITCAST:
2407 case ISD::BSWAP:
2409 case ISD::CTPOP:
2411 case ISD::CTLZ:
2412 case ISD::CTLZ_ZERO_UNDEF:
2414 case ISD::CTTZ:
2415 case ISD::CTTZ_ZERO_UNDEF:
2425 case ISD::FNEG:
2428 case ISD::FABS:
2431 case ISD::FP_EXTEND: {
2439 case ISD::FP_TO_SINT:
2440 case ISD::FP_TO_UINT: {
2446 Opcode==ISD::FP_TO_SINT,
2453 case ISD::BITCAST:
2465 case ISD::TokenFactor:
2466 case ISD::MERGE_VALUES:
2467 case ISD::CONCAT_VECTORS:
2469 case ISD::FP_ROUND: llvm_unreachable("Invalid method to make FP_ROUND node");
2470 case ISD::FP_EXTEND:
2478 if (Operand.getOpcode() == ISD::UNDEF)
2481 case ISD::SIGN_EXTEND:
2491 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND)
2493 else if (OpOpcode == ISD::UNDEF)
2497 case ISD::ZERO_EXTEND:
2507 if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x)
2508 return getNode(ISD::ZERO_EXTEND, DL, VT,
2510 else if (OpOpcode == ISD::UNDEF)
2514 case ISD::ANY_EXTEND:
2525 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND ||
2526 OpOpcode == ISD::ANY_EXTEND)
2529 else if (OpOpcode == ISD::UNDEF)
2533 if (OpOpcode == ISD::TRUNCATE) {
2539 case ISD::TRUNCATE:
2549 if (OpOpcode == ISD::TRUNCATE)
2550 return getNode(ISD::TRUNCATE, DL, VT, Operand.getNode()->getOperand(0));
2551 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND ||
2552 OpOpcode == ISD::ANY_EXTEND) {
2558 return getNode(ISD::TRUNCATE, DL, VT, Operand.getNode()->getOperand(0));
2561 if (OpOpcode == ISD::UNDEF)
2564 case ISD::BITCAST:
2569 if (OpOpcode == ISD::BITCAST) // bitconv(bitconv(x)) -> bitconv(x)
2570 return getNode(ISD::BITCAST, DL, VT, Operand.getOperand(0));
2571 if (OpOpcode == ISD::UNDEF)
2574 case ISD::SCALAR_TO_VECTOR:
2581 if (OpOpcode == ISD::UNDEF)
2584 if (OpOpcode == ISD::EXTRACT_VECTOR_ELT &&
2590 case ISD::FNEG:
2592 if (getTarget().Options.UnsafeFPMath && OpOpcode == ISD::FSUB)
2593 return getNode(ISD::FSUB, DL, VT, Operand.getNode()->getOperand(1),
2595 if (OpOpcode == ISD::FNEG) // --X -> X
2598 case ISD::FABS:
2599 if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X)
2600 return getNode(ISD::FABS, DL, VT, Operand.getNode()->getOperand(0));
2634 case ISD::ADD: return getConstant(C1 + C2, VT);
2635 case ISD
2636 case ISD::MUL: return getConstant(C1 * C2, VT);
2637 case ISD::UDIV:
2640 case ISD::UREM:
2643 case ISD::SDIV:
2646 case ISD::SREM:
2649 case ISD::AND: return getConstant(C1 & C2, VT);
2650 case ISD::OR: return getConstant(C1 | C2, VT);
2651 case ISD::XOR: return getConstant(C1 ^ C2, VT);
2652 case ISD::SHL: return getConstant(C1 << C2, VT);
2653 case ISD::SRL: return getConstant(C1.lshr(C2), VT);
2654 case ISD::SRA: return getConstant(C1.ashr(C2), VT);
2655 case ISD::ROTL: return getConstant(C1.rotl(C2), VT);
2656 case ISD::ROTR: return getConstant(C1.rotr(C2), VT);
2669 case ISD::TokenFactor:
2673 if (N1.getOpcode() == ISD::EntryToken) return N2;
2674 if (N2.getOpcode() == ISD::EntryToken) return N1;
2677 case ISD::CONCAT_VECTORS:
2680 if (N1.getOpcode() == ISD::BUILD_VECTOR &&
2681 N2.getOpcode() == ISD::BUILD_VECTOR) {
2685 return getNode(ISD::BUILD_VECTOR, DL, VT, &Elts[0], Elts.size());
2688 case ISD::AND:
2699 case ISD::OR:
2700 case ISD::XOR:
2701 case ISD::ADD:
2702 case ISD::SUB:
2711 case ISD::UDIV:
2712 case ISD::UREM:
2713 case ISD::MULHU:
2714 case ISD::MULHS:
2715 case ISD::MUL:
2716 case ISD::SDIV:
2717 case ISD::SREM:
2722 case ISD::FADD:
2723 case ISD::FSUB:
2724 case ISD::FMUL:
2725 case ISD::FDIV:
2726 case ISD::FREM:
2728 if (Opcode == ISD::FADD) {
2737 } else if (Opcode == ISD::FSUB) {
2748 case ISD::FCOPYSIGN: // N1 and result must match. N1/N2 need not match.
2754 case ISD::SHL:
2755 case ISD::SRA:
2756 case ISD::SRL:
2757 case ISD::ROTL:
2758 case ISD::ROTR:
2779 case ISD::FP_ROUND_INREG: {
2795 case ISD::FP_ROUND:
2802 case ISD::AssertSext:
2803 case ISD::AssertZext: {
2815 case ISD::SIGN_EXTEND_INREG: {
2838 case ISD::EXTRACT_VECTOR_ELT:
2840 if (N1.getOpcode() == ISD::UNDEF)
2846 N1.getOpcode() == ISD::CONCAT_VECTORS &&
2850 return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
2858 if (N2C && N1.getOpcode() == ISD::BUILD_VECTOR) {
2864 Elt = getNode(ISD::TRUNCATE, DL, VEltTy, Elt);
2869 Elt = getNode(ISD::ANY_EXTEND, DL, VT, Elt);
2876 if (N1.getOpcode() == ISD::INSERT_VECTOR_ELT) {
2891 return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, N1.getOperand(0), N2);
2895 case ISD::EXTRACT_ELEMENT:
2905 if (N1.getOpcode() == ISD::BUILD_PAIR)
2916 case ISD::EXTRACT_SUBVECTOR: {
2965 case ISD::FADD:
2970 case ISD::FSUB:
2975 case ISD::FMUL:
2980 case ISD::FDIV:
2985 case ISD::FREM :
2990 case ISD::FCOPYSIGN:
2997 if (Opcode == ISD::FP_ROUND) {
3009 if (N1.getOpcode() == ISD::UNDEF) {
3014 case ISD::FP_ROUND_INREG:
3015 case ISD::SIGN_EXTEND_INREG:
3016 case ISD::SUB:
3017 case ISD::FSUB:
3018 case ISD::FDIV:
3019 case ISD::FREM:
3020 case ISD::SRA:
3022 case ISD::UDIV:
3023 case ISD::SDIV:
3024 case ISD::UREM:
3025 case ISD::SREM:
3026 case ISD::SRL:
3027 case ISD::SHL:
3038 if (N2.getOpcode() == ISD::UNDEF) {
3040 case ISD::XOR:
3041 if (N1.getOpcode() == ISD::UNDEF)
3046 case ISD::ADD:
3047 case ISD::ADDC:
3048 case ISD::ADDE:
3049 case ISD::SUB:
3050 case ISD::UDIV:
3051 case ISD::SDIV:
3052 case ISD::UREM:
3053 case ISD::SREM:
3055 case ISD::FADD:
3056 case ISD::FSUB:
3057 case ISD::FMUL:
3058 case ISD::FDIV:
3059 case ISD::FREM:
3063 case ISD::MUL:
3064 case ISD::AND:
3065 case ISD::SRL:
3066 case ISD::SHL:
3072 case ISD::OR:
3078 case ISD::SRA:
3112 case ISD::CONCAT_VECTORS:
3115 if (N1.getOpcode() == ISD::BUILD_VECTOR &&
3116 N2.getOpcode() == ISD::BUILD_VECTOR &&
3117 N3.getOpcode() == ISD::BUILD_VECTOR) {
3122 return getNode(ISD::BUILD_VECTOR, DL, VT, &Elts[0], Elts.size());
3125 case ISD::SETCC: {
3131 case ISD::SELECT:
3140 case ISD::VECTOR_SHUFFLE:
3142 case ISD::INSERT_SUBVECTOR: {
3166 case ISD::BITCAST:
3230 return getNode(ISD::TokenFactor, Chain.getDebugLoc(), MVT::Other,
3249 assert(Value.getOpcode() != ISD::UNDEF);
3259 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Value);
3264 Value = DAG.getNode(ISD::MUL, dl, VT, Value, DAG.getConstant(Magic, VT));
3284 return DAG.getNode(ISD::BITCAST, dl, VT,
3312 return DAG.getNode(ISD::ADD, Base.getDebugLoc(),
3321 if (Src.getOpcode() == ISD::GlobalAddress)
3323 else if (Src.getOpcode() == ISD::ADD &&
3324 Src.getOperand(0).getOpcode() == ISD::GlobalAddress &&
3325 Src.getOperand(1).getOpcode() == ISD::Constant) {
3416 if (Src.getOpcode() == ISD::UNDEF)
3485 Value = DAG.getExtLoad(ISD::EXTLOAD, dl, NVT, Chain,
3499 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3511 if (Src.getOpcode() == ISD::UNDEF)
3564 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3579 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3589 if (Src.getOpcode() == ISD::UNDEF)
3641 Value = DAG.getNode(ISD::TRUNCATE, dl, VT, MemSetValue);
3654 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3813 Src = getNode(ISD::TRUNCATE, dl, MVT::i32, Src);
3815 Src = getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Src);
3867 assert(Opcode == ISD::ATOMIC_CMP_SWAP && "Invalid Atomic Op");
3905 if (Opcode != ISD::ATOMIC_STORE || Ordering > Monotonic)
3927 assert((Opcode == ISD::ATOMIC_LOAD_ADD ||
3928 Opcode == ISD::ATOMIC_LOAD_SUB ||
3929 Opcode == ISD::ATOMIC_LOAD_AND ||
3930 Opcode == ISD::ATOMIC_LOAD_OR ||
3931 Opcode == ISD::ATOMIC_LOAD_XOR ||
3932 Opcode == ISD::ATOMIC_LOAD_NAND ||
3933 Opcode == ISD::ATOMIC_LOAD_MIN ||
3934 Opcode == ISD::ATOMIC_LOAD_MAX ||
3935 Opcode == ISD::ATOMIC_LOAD_UMIN ||
3936 Opcode == ISD::ATOMIC_LOAD_UMAX ||
3937 Opcode == ISD::ATOMIC_SWAP ||
3938 Opcode == ISD::ATOMIC_STORE) &&
3943 SDVTList VTs = Opcode == ISD::ATOMIC_STORE ? getVTList(MVT::Other) :
3998 assert(Opcode == ISD::ATOMIC_LOAD && "Invalid Atomic Op");
4027 return getNode(ISD::MERGE_VALUES, dl, getVTList(&VTs[0], NumOps),
4070 assert((Opcode == ISD::INTRINSIC_VOID ||
4071 Opcode == ISD::INTRINSIC_W_CHAIN ||
4072 Opcode == ISD::PREFETCH ||
4074 (int)Opcode >= ISD::FIRST_TARGET_MEMORY_OPCODE)) &&
4109 if (Ptr.getOpcode() != ISD::ADD ||
4127 if (OffsetOp.getOpcode() == ISD::UNDEF)
4134 SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
4167 SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
4172 ExtType = ISD::NON_EXTLOAD;
4173 } else if (ExtType == ISD::NON_EXTLOAD) {
4188 bool Indexed = AM != ISD::UNINDEXED;
4189 assert((Indexed || Offset.getOpcode() == ISD::UNDEF) &&
4196 AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3);
4221 return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, dl, Chain, Ptr, Undef,
4226 SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, EVT VT,
4232 return getLoad(ISD::UNINDEXED, ExtType, VT, dl, Chain, Ptr, Undef,
4240 SDValue Offset, ISD::MemIndexedMode AM) {
4242 assert(LD->getOffset().getOpcode() == ISD::UNDEF &&
4286 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
4288 ID.AddInteger(encodeMemSDNodeFlags(false, ISD
4295 SDNode *N = new (NodeAllocator) StoreSDNode(Ops, dl, VTs, ISD::UNINDEXED,
4353 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
4355 ID.AddInteger(encodeMemSDNodeFlags(true, ISD::UNINDEXED, MMO->isVolatile(),
4362 SDNode *N = new (NodeAllocator) StoreSDNode(Ops, dl, VTs, ISD::UNINDEXED,
4371 SDValue Offset, ISD::MemIndexedMode AM) {
4373 assert(ST->getOffset().getOpcode() == ISD::UNDEF &&
4378 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
4399 return getNode(ISD::VAARG, dl, getVTList(VT, MVT::Other), Ops, 4);
4430 case ISD::SELECT_CC: {
4440 case ISD::BR_CC: {
4498 case ISD::SRA_PARTS:
4499 case ISD::SRL_PARTS:
4500 case ISD::SHL_PARTS:
4501 if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG &&
4504 else if (N3.getOpcode() == ISD::AND)
5619 assert(AllNodes.front().getOpcode() == ISD::EntryToken &&
5694 SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, MMO->isVolatile(),
5707 SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, MMO->isVolatile(),
5827 if (getOpcode() == ISD::TokenFactor) {
5910 Operands[j] = getNode(ISD::EXTRACT_VECTOR_ELT, dl,
5925 case ISD::VSELECT:
5926 Scalars.push_back(getNode(ISD::SELECT, dl, EltVT,
5929 case ISD::SHL:
5930 case ISD::SRA:
5931 case ISD::SRL:
5932 case ISD::ROTL:
5933 case ISD::ROTR:
5938 case ISD::SIGN_EXTEND_INREG:
5939 case ISD::FP_ROUND_INREG: {
5951 return getNode(ISD::BUILD_VECTOR, dl,
5970 if (Loc.getOpcode() == ISD::FrameIndex) {
5971 if (BaseLoc.getOpcode() != ISD::FrameIndex)
6067 // of the vector is an ISD::UNDEF value) are set in SplatUndef and cleared
6079 if (OpVal.getOpcode() == ISD::UNDEF)
