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Lines Matching refs:AssertZext

95 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
214 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
694       // now, just use the tightest assertzext/assertsext possible.
718       Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
4387   if (Ext.getOpcode() == ISD::AssertZext || Ext.getOpcode() == ISD::AssertSext){
6506     AssertOp = ISD::AssertZext;
6733           AssertOp = ISD::AssertZext;