Lines Matching refs:RegState
305 .addReg(Op0, Op0IsKill * RegState::Kill));
308 .addReg(Op0, Op0IsKill * RegState::Kill));
325 .addReg(Op0, Op0IsKill * RegState::Kill)
326 .addReg(Op1, Op1IsKill * RegState::Kill));
329 .addReg(Op0, Op0IsKill * RegState::Kill)
330 .addReg(Op1, Op1IsKill * RegState::Kill));
348 .addReg(Op0, Op0IsKill * RegState::Kill)
349 .addReg(Op1, Op1IsKill * RegState::Kill)
350 .addReg(Op2, Op2IsKill * RegState::Kill));
353 .addReg(Op0, Op0IsKill * RegState::Kill)
354 .addReg(Op1, Op1IsKill * RegState::Kill)
355 .addReg(Op2, Op2IsKill * RegState::Kill));
372 .addReg(Op0, Op0IsKill * RegState::Kill)
376 .addReg(Op0, Op0IsKill * RegState::Kill)
394 .addReg(Op0, Op0IsKill * RegState::Kill)
398 .addReg(Op0, Op0IsKill * RegState::Kill)
417 .addReg(Op0, Op0IsKill * RegState::Kill)
418 .addReg(Op1, Op1IsKill * RegState::Kill)
422 .addReg(Op0, Op0IsKill * RegState::Kill)
423 .addReg(Op1, Op1IsKill * RegState::Kill)
1962 .addReg(NextVA.getLocReg(), RegState::Define)
