Lines Matching refs:ARMISD
458 if (N.getOpcode() == ARMISD::Wrapper &&
625 } else if (N.getOpcode() == ARMISD::Wrapper &&
881 } else if (N.getOpcode() == ARMISD::Wrapper &&
956 if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
996 if (N.getOpcode() == ARMISD::Wrapper &&
1052 if (N.getOpcode() == ARMISD::Wrapper &&
1058 if (N.getOpcode() == ARMISD::Wrapper &&
1192 if (N.getOpcode() == ARMISD::Wrapper &&
2388 case ARMISD::CAND: Opc = ARM::t2ANDCCrs; break;
2389 case ARMISD::COR: Opc = ARM::t2ORRCCrs; break;
2390 case ARMISD::CXOR: Opc = ARM::t2EORCCrs; break;
2403 case ARMISD::CAND: Opc = ARM::t2ANDCCri; break;
2404 case ARMISD::COR: Opc = ARM::t2ORRCCri; break;
2405 case ARMISD::CXOR: Opc = ARM::t2EORCCri; break;
2416 case ARMISD::CAND: Opc = ARM::t2ANDCCrr; break;
2417 case ARMISD::COR: Opc = ARM::t2ORRCCrr; break;
2418 case ARMISD::CXOR: Opc = ARM::t2EORCCrr; break;
2431 case ARMISD::CAND: Opc = ARM::ANDCCrsi; break;
2432 case ARMISD::COR: Opc = ARM::ORRCCrsi; break;
2433 case ARMISD::CXOR: Opc = ARM::EORCCrsi; break;
2443 case ARMISD::CAND: Opc = ARM::ANDCCrsr; break;
2444 case ARMISD::COR: Opc = ARM::ORRCCrsr; break;
2445 case ARMISD::CXOR: Opc = ARM::EORCCrsr; break;
2458 case ARMISD::CAND: Opc = ARM::ANDCCri; break;
2459 case ARMISD::COR: Opc = ARM::ORRCCri; break;
2460 case ARMISD::CXOR: Opc = ARM::EORCCri; break;
2471 case ARMISD::CAND: Opc = ARM::ANDCCrr; break;
2472 case ARMISD::COR: Opc = ARM::ORRCCrr; break;
2473 case ARMISD::CXOR: Opc = ARM::EORCCrr; break;
2727 case ARMISD::VMOVRRD:
2775 case ARMISD::BRCOND: {
2814 case ARMISD::CMOV:
2816 case ARMISD::CAND:
2817 case ARMISD::COR:
2818 case ARMISD::CXOR:
2820 case ARMISD::VZIP: {
2840 case ARMISD::VUZP: {
2860 case ARMISD::VTRN: {
2879 case ARMISD::BUILD_VECTOR: {
2895 case ARMISD::VLD2DUP: {
2901 case ARMISD::VLD3DUP: {
2907 case ARMISD::VLD4DUP: {
2913 case ARMISD::VLD2DUP_UPD: {
2919 case ARMISD::VLD3DUP_UPD: {
2925 case ARMISD::VLD4DUP_UPD: {
2931 case ARMISD::VLD1_UPD: {
2941 case ARMISD::VLD2_UPD: {
2952 case ARMISD::VLD3_UPD: {
2964 case ARMISD::VLD4_UPD: {
2976 case ARMISD::VLD2LN_UPD: {
2984 case ARMISD::VLD3LN_UPD: {
2992 case ARMISD::VLD4LN_UPD: {
3000 case ARMISD::VST1_UPD: {
3010 case ARMISD::VST2_UPD: {
3021 case ARMISD::VST3_UPD: {
3033 case ARMISD::VST4_UPD: {
3045 case ARMISD::VST2LN_UPD: {
3053 case ARMISD::VST3LN_UPD: {
3061 case ARMISD::VST4LN_UPD: {
3329 case ARMISD::VTBL1: {
3340 case ARMISD::VTBL2: {
3361 case ARMISD::ATOMOR64_DAG:
3363 case ARMISD::ATOMXOR64_DAG:
3365 case ARMISD::ATOMADD64_DAG:
3367 case ARMISD::ATOMSUB64_DAG:
3369 case ARMISD::ATOMNAND64_DAG:
3371 case ARMISD::ATOMAND64_DAG:
3373 case ARMISD::ATOMSWAP64_DAG:
3375 case ARMISD::ATOMCMPXCHG64_DAG:
