Lines Matching refs:isUpdating
212 SDNode *SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
220 SDNode *SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
228 bool isUpdating, unsigned NumVecs,
234 SDNode *SelectVLDDup(SDNode *N, bool isUpdating, unsigned NumVecs,
1599 SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
1606 unsigned AddrOpIdx = isUpdating ? 1 : 2;
1645 if (isUpdating)
1660 if (isUpdating) {
1694 if (isUpdating) {
1726 if (isUpdating)
1731 SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
1738 unsigned AddrOpIdx = isUpdating ? 1 : 2;
1739 unsigned Vec0Idx = 3; // AddrOpIdx + (isUpdating ? 2 : 1)
1771 if (isUpdating)
1810 if (isUpdating) {
1859 if (isUpdating) {
1877 bool isUpdating, unsigned NumVecs,
1884 unsigned AddrOpIdx = isUpdating ? 1 : 2;
1885 unsigned Vec0Idx = 3; // AddrOpIdx + (isUpdating ? 2 : 1)
1935 if (isUpdating)
1945 if (isUpdating) {
1991 if (isUpdating)
1996 SDNode *ARMDAGToDAGISel::SelectVLDDup(SDNode *N, bool isUpdating,
2042 if (isUpdating) {
2059 if (isUpdating)
2074 if (isUpdating)
