Lines Matching defs:N0
4803 SDNode *N0 = N->getOperand(0).getNode();
4805 return N0->hasOneUse() && N1->hasOneUse() &&
4806 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
4814 SDNode *N0 = N->getOperand(0).getNode();
4816 return N0->hasOneUse() && N1->hasOneUse() &&
4817 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
4827 SDNode *N0 = Op.getOperand(0).getNode();
4831 bool isN0SExt = isSignExtended(N0, DAG);
4836 bool isN0ZExt = isZeroExtended(N0, DAG);
4843 if (isN1SExt && isAddSubSExt(N0, DAG)) {
4846 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
4850 std::swap(N0, N1);
4871 Op0 = SkipExtension(N0, DAG);
4886 SDValue N00 = SkipExtension(N0->getOperand(0).getNode(), DAG);
4887 SDValue N01 = SkipExtension(N0->getOperand(1).getNode(), DAG);
4889 return DAG.getNode(N0->getOpcode(), DL, VT,
4926 LowerSDIV_v4i16(SDValue N0, SDValue N1, DebugLoc dl, SelectionDAG &DAG) {
4931 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0);
4933 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
4949 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
4950 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
4953 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
4954 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
4957 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
4958 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
4959 return N0;
4968 SDValue N0 = Op.getOperand(0);
4973 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0);
4976 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4980 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4985 N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16
4988 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
4989 N0 = LowerCONCAT_VECTORS(N0, DAG);
4991 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0);
4992 return N0;
4994 return LowerSDIV_v4i16(N0, N1, dl, DAG);
5003 SDValue N0 = Op.getOperand(0);
5008 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0);
5011 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
5015 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
5020 N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16
5023 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
5024 N0 = LowerCONCAT_VECTORS(N0, DAG);
5026 N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8,
5028 N0);
5029 return N0;
5035 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0);
5037 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
5058 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
5059 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
5062 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
5063 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
5066 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
5067 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
5068 return N0;
6711 static SDValue AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1,
6718 || N0.getOpcode() != ISD::BUILD_VECTOR
6728 // N0 and N1 are BUILD_VECTOR nodes with N number of EXTRACT_VECTOR
6734 if (N0->getOperand(0)->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
6736 SDValue Vec = N0->getOperand(0)->getOperand(0);
6743 for (unsigned i = 0, e = N0->getNumOperands(); i != e; ++i) {
6744 if (N0->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT
6747 SDValue ExtVec0 = N0->getOperand(i);
6799 /// operands N0 and N1. This is a helper for PerformADDCombine that is
6802 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
6807 SDValue Result = AddCombineToVPADDL(N, N0, N1, DCI, Subtarget);
6812 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
6813 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
6824 SDValue N0 = N->getOperand(0);
6828 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget);
6833 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget);
6840 SDValue N0 = N->getOperand(0);
6845 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
6867 SDValue N0 = N->getOperand(0);
6869 unsigned Opcode = N0.getOpcode();
6876 std::swap(N0, N1);
6881 SDValue N00 = N0->getOperand(0);
6882 SDValue N01 = N0->getOperand(1);
6990 SDValue N0 = N->getOperand(0);
6996 isCand = isCMOVWithZeroOrAllOnesLHS(N0, isAND);
6998 std::swap(N0, N1);
7010 return DAG.getNode(Opc, N->getDebugLoc(), N->getValueType(0), N0,
7098 SDValue N0 = N->getOperand(0);
7099 if (N0.getOpcode() != ISD::AND)
7110 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(1));
7122 N0->getOperand(1), N0->getOperand(0),
7150 SDValue N00 = N0.getOperand(0);
7155 SDValue MaskOp = N0.getOperand(1);
7905 SDValue N0 = Op->getOperand(0);
7917 DAG.getConstant(IntrinsicOpcode, MVT::i32), N0,
8179 SDValue N0 = N->getOperand(0);
8180 if (C->getZExtValue() == 16 && N0.getOpcode() == ISD::BSWAP &&
8181 DAG.MaskedValueIsZero(N0.getOperand(0),
8183 return DAG.getNode(ISD::ROTR, N->getDebugLoc(), VT, N0, N1);
8220 SDValue N0 = N->getOperand(0);
8226 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
8227 SDValue Vec = N0.getOperand(0);
8228 SDValue Lane = N0.getOperand(1);
8230 EVT EltVT = N0.getValueType();
