Lines Matching refs:ARMISD
779 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
794 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
880 case ARMISD::Wrapper: return "ARMISD::Wrapper";
881 case ARMISD::WrapperDYN: return "ARMISD::WrapperDYN";
882 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC";
883 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
884 case ARMISD::CALL: return "ARMISD::CALL";
885 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
886 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
887 case ARMISD::tCALL: return "ARMISD::tCALL";
888 case ARMISD::BRCOND: return "ARMISD::BRCOND";
889 case ARMISD::BR_JT: return "ARMISD::BR_JT";
890 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
891 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
892 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
893 case ARMISD::CMP: return "ARMISD::CMP";
894 case ARMISD::CMPZ: return "ARMISD::CMPZ";
895 case ARMISD::CMPFP: return "ARMISD::CMPFP";
896 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
897 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
898 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
900 case ARMISD::CMOV: return "ARMISD::CMOV";
901 case ARMISD::CAND: return "ARMISD::CAND";
902 case ARMISD::COR: return "ARMISD::COR";
903 case ARMISD::CXOR: return "ARMISD::CXOR";
905 case ARMISD::RBIT: return "ARMISD::RBIT";
907 case ARMISD::FTOSI: return "ARMISD::FTOSI";
908 case ARMISD::FTOUI: return "ARMISD::FTOUI";
909 case ARMISD::SITOF: return "ARMISD::SITOF";
910 case ARMISD::UITOF: return "ARMISD::UITOF";
912 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
913 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
914 case ARMISD::RRX: return "ARMISD::RRX";
916 case ARMISD::ADDC: return "ARMISD::ADDC";
917 case ARMISD::ADDE: return "ARMISD::ADDE";
918 case ARMISD::SUBC: return "ARMISD::SUBC";
919 case ARMISD::SUBE: return "ARMISD::SUBE";
921 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
922 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
924 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
925 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
927 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
929 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
931 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
933 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER";
934 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
936 case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
938 case ARMISD::VCEQ: return "ARMISD::VCEQ";
939 case ARMISD::VCEQZ: return "ARMISD::VCEQZ";
940 case ARMISD::VCGE: return "ARMISD::VCGE";
941 case ARMISD::VCGEZ: return "ARMISD::VCGEZ";
942 case ARMISD::VCLEZ: return "ARMISD::VCLEZ";
943 case ARMISD::VCGEU: return "ARMISD::VCGEU";
944 case ARMISD::VCGT: return "ARMISD::VCGT";
945 case ARMISD::VCGTZ: return "ARMISD::VCGTZ";
946 case ARMISD::VCLTZ: return "ARMISD::VCLTZ";
947 case ARMISD::VCGTU: return "ARMISD::VCGTU";
948 case ARMISD::VTST: return "ARMISD::VTST";
950 case ARMISD::VSHL: return "ARMISD::VSHL";
951 case ARMISD::VSHRs: return "ARMISD::VSHRs";
952 case ARMISD::VSHRu: return "ARMISD::VSHRu";
953 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
954 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
955 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
956 case ARMISD::VSHRN: return "ARMISD::VSHRN";
957 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
958 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
959 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
960 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
961 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
962 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
963 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
964 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
965 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
966 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
967 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
968 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
969 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
970 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
971 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
972 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
973 case ARMISD::VMOVFPIMM: return "ARMISD::VMOVFPIMM";
974 case ARMISD::VDUP: return "ARMISD::VDUP";
975 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
976 case ARMISD::VEXT: return "ARMISD::VEXT";
977 case ARMISD::VREV64: return "ARMISD::VREV64";
978 case ARMISD::VREV32: return "ARMISD::VREV32";
979 case ARMISD::VREV16: return "ARMISD::VREV16";
980 case ARMISD::VZIP: return "ARMISD::VZIP";
981 case ARMISD::VUZP: return "ARMISD::VUZP";
982 case ARMISD::VTRN: return "ARMISD::VTRN";
983 case ARMISD::VTBL1: return "ARMISD::VTBL1";
984 case ARMISD::VTBL2: return "ARMISD::VTBL2";
985 case ARMISD::VMULLs: return "ARMISD::VMULLs";
986 case ARMISD::VMULLu: return "ARMISD::VMULLu";
987 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
988 case ARMISD::FMAX: return "ARMISD::FMAX";
989 case ARMISD::FMIN: return "ARMISD::FMIN";
990 case ARMISD::BFI: return "ARMISD::BFI";
991 case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
992 case ARMISD::VBICIMM: return "ARMISD::VBICIMM";
993 case ARMISD::VBSL: return "ARMISD::VBSL";
994 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP";
995 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP";
996 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP";
997 case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD";
998 case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD";
999 case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD";
1000 case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD";
1001 case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD";
1002 case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD";
1003 case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD";
1004 case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD";
1005 case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD";
1006 case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD";
1007 case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD";
1008 case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD";
1009 case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD";
1010 case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD";
1011 case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD";
1012 case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD";
1013 case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD";
1205 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1220 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1268 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1286 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1499 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1514 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1535 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1541 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1564 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1570 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1586 CallOpc = ARMISD::CALL_NOLINK;
1590 CallOpc = ARMISD::CALL_NOLINK;
1592 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1595 CallOpc = ARMISD::CALL_NOLINK;
1598 CallOpc = ARMISD::CALL_NOLINK;
1600 CallOpc = isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL;
1624 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
1898 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
1915 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1932 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1934 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
1953 } else if (Copy->getOpcode() == ARMISD::VMOVRRD) {
1991 if (UI->getOpcode() != ARMISD::RET_FLAG)
2014 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
2031 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
2058 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
2065 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
2082 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
2089 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
2118 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2131 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2138 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
2148 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2185 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2206 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
2210 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2233 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
2237 ? ARMISD::WrapperPIC : ARMISD::WrapperDYN;
2259 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2268 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2292 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2297 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2304 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl,
2312 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
2325 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2341 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2349 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2356 ? ARMISD::VMULLs : ARMISD::VMULLu;
2372 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
2387 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0),
2402 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
2406 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0),
2432 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
2483 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
2724 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
2779 ARMISD::NodeType CompareType;
2782 CompareType = ARMISD::CMP;
2787 CompareType = ARMISD::CMPZ;
2800 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS);
2802 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS);
2803 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
2812 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
2815 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation");
2818 if (Opc == ARMISD::CMPFP)
2821 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT");
2824 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
2838 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
2864 return DAG.getNode(ARMISD::CMOV, dl, VT, True, False, ARMcc, CCR, Cmp);
2892 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,Cmp);
2901 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
2907 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
3013 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
3027 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops, 7);
3045 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
3067 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
3071 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
3087 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
3095 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
3104 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
3110 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
3144 Opc = ARMISD::FTOSI;
3147 Opc = ARMISD::FTOUI;
3198 Opc = ARMISD::SITOF;
3201 Opc = ARMISD::UITOF;
3217 Tmp0.getOpcode() == ARMISD::VMOVDRR;
3223 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
3227 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT,
3235 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT,
3239 Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64,
3247 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
3267 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
3283 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
3288 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
3353 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
3358 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
3378 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
3411 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc,
3445 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc,
3478 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
3545 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
3548 // The low part is an ARMISD::RRX operand, which shifts the carry in.
3549 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
3574 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
3578 case ISD::SETGT: Opc = ARMISD::VCGT; break;
3582 case ISD::SETGE: Opc = ARMISD::VCGE; break;
3584 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
3586 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
3593 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3594 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
3602 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3603 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
3611 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
3613 case ISD::SETGT: Opc = ARMISD::VCGT; break;
3615 case ISD::SETGE: Opc = ARMISD::VCGE; break;
3617 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
3619 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
3623 if (Opc == ARMISD::VCEQ) {
3636 Opc = ARMISD::VTST;
3653 if (Opc == ARMISD::VCGE)
3654 Opc = ARMISD::VCLEZ;
3655 else if (Opc == ARMISD::VCGT)
3656 Opc = ARMISD::VCLTZ;
3663 case ARMISD::VCEQ:
3664 Result = DAG.getNode(ARMISD::VCEQZ, dl, VT, SingleOp); break;
3665 case ARMISD::VCGE:
3666 Result = DAG.getNode(ARMISD::VCGEZ, dl, VT, SingleOp); break;
3667 case ARMISD::VCLEZ:
3668 Result = DAG.getNode(ARMISD::VCLEZ, dl, VT, SingleOp); break;
3669 case ARMISD::VCGT:
3670 Result = DAG.getNode(ARMISD::VCGTZ, dl, VT, SingleOp); break;
3671 case ARMISD::VCLTZ:
3672 Result = DAG.getNode(ARMISD::VCLTZ, dl, VT, SingleOp); break;
3837 SDValue VecConstant = DAG.getNode(ARMISD::VMOVFPIMM, DL, MVT::v2f32,
3850 SDValue VecConstant = DAG.getNode(ARMISD::VMOVIMM, DL, VMovVT,
3863 SDValue VecConstant = DAG.getNode(ARMISD::VMVNIMM, DL, VMovVT, NewVal);
4113 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
4124 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
4133 return DAG.getNode(ARMISD::VMOVFPIMM, dl, VT, Val);
4172 return DAG.getNode(ARMISD::VDUP, dl, VT, Value);
4186 return DAG.getNode(ARMISD::VDUP, dl, VT, Val);
4203 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
4213 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
4326 ShuffleSrcs[i] = DAG.getNode(ARMISD::VEXT, dl, VT, VEXTSrc1, VEXTSrc2,
4448 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
4451 return DAG.getNode(ARMISD::VREV32, dl, VT, OpLHS);
4454 return DAG.getNode(ARMISD::VREV16, dl, VT, OpLHS);
4459 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
4464 return DAG.getNode(ARMISD::VEXT, dl, VT,
4469 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4473 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4477 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4496 return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1,
4500 return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2,
4529 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
4543 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
4545 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
4554 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
4559 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
4561 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
4563 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
4572 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4575 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4578 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4582 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4585 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4588 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4614 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
4632 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
4664 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
4834 NewOpc = ARMISD::VMULLs;
4839 NewOpc = ARMISD::VMULLu;
4844 NewOpc = ARMISD::VMULLs;
4847 NewOpc = ARMISD::VMULLu;
4851 NewOpc = ARMISD::VMULLu;
5079 case ISD::ADDC: Opc = ARMISD::ADDC; break;
5080 case ISD::ADDE: Opc = ARMISD::ADDE; ExtraOp = true; break;
5081 case ISD::SUBC: Opc = ARMISD::SUBC; break;
5082 case ISD::SUBE: Opc = ARMISD::SUBE; ExtraOp = true; break;
5119 if (NewOp == ARMISD::ATOMCMPXCHG64_DAG) {
5210 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMADD64_DAG);
5213 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMAND64_DAG);
5216 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMNAND64_DAG);
5219 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMOR64_DAG);
5222 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMSUB64_DAG);
5225 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMXOR64_DAG);
5228 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMSWAP64_DAG);
5231 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMCMPXCHG64_DAG);
6973 if (N.getOpcode() != ARMISD::CMOV || !N.getNode()->hasOneUse())
7006 case ISD::AND: Opc = ARMISD::CAND; break;
7007 case ISD::OR: Opc = ARMISD::COR; break;
7008 case ISD::XOR: Opc = ARMISD::CXOR; break;
7042 SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val);
7085 SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val);
7121 SDValue Result = DAG.getNode(ARMISD::VBSL, dl, CanonicalVT,
7173 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00,
7201 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res,
7217 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
7236 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0),
7280 return DCI.DAG.getNode(ARMISD::BFI, N->getDebugLoc(), N->getValueType(0),
7288 /// ARMISD::VMOVRRD.
7293 if (InDouble.getOpcode() == ARMISD::VMOVDRR)
7331 /// ARMISD::VMOVDRR. This is also used for BUILD_VECTORs with 2 operands.
7340 if (Op0.getOpcode() == ARMISD::VMOVRRD &&
7443 if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR &&
7505 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X):
7649 case Intrinsic::arm_neon_vld1: NewOpc = ARMISD::VLD1_UPD;
7651 case Intrinsic::arm_neon_vld2: NewOpc = ARMISD::VLD2_UPD;
7653 case Intrinsic::arm_neon_vld3: NewOpc = ARMISD::VLD3_UPD;
7655 case Intrinsic::arm_neon_vld4: NewOpc = ARMISD::VLD4_UPD;
7657 case Intrinsic::arm_neon_vld2lane: NewOpc = ARMISD::VLD2LN_UPD;
7659 case Intrinsic::arm_neon_vld3lane: NewOpc = ARMISD::VLD3LN_UPD;
7661 case Intrinsic::arm_neon_vld4lane: NewOpc = ARMISD::VLD4LN_UPD;
7663 case Intrinsic::arm_neon_vst1: NewOpc = ARMISD::VST1_UPD;
7665 case Intrinsic::arm_neon_vst2: NewOpc = ARMISD::VST2_UPD;
7667 case Intrinsic::arm_neon_vst3: NewOpc = ARMISD::VST3_UPD;
7669 case Intrinsic::arm_neon_vst4: NewOpc = ARMISD::VST4_UPD;
7671 case Intrinsic::arm_neon_vst2lane: NewOpc = ARMISD::VST2LN_UPD;
7673 case Intrinsic::arm_neon_vst3lane: NewOpc = ARMISD::VST3LN_UPD;
7675 case Intrinsic::arm_neon_vst4lane: NewOpc = ARMISD::VST4LN_UPD;
7682 case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break;
7683 case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break;
7684 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break;
7766 NewOpc = ARMISD::VLD2DUP;
7769 NewOpc = ARMISD::VLD3DUP;
7772 NewOpc = ARMISD::VLD4DUP;
7787 if (User->getOpcode() != ARMISD::VDUPLANE ||
7828 /// ARMISD::VDUPLANE.
7842 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
8043 VShiftOpc = ARMISD::VSHL;
8048 ARMISD::VSHRs : ARMISD::VSHRu);
8102 VShiftOpc = ARMISD::VSHLLi;
8105 ARMISD::VSHLLs : ARMISD::VSHLLu);
8108 VShiftOpc = ARMISD::VSHRN; break;
8110 VShiftOpc = ARMISD::VRSHRs; break;
8112 VShiftOpc = ARMISD::VRSHRu; break;
8114 VShiftOpc = ARMISD::VRSHRN; break;
8116 VShiftOpc = ARMISD::VQSHLs; break;
8118 VShiftOpc = ARMISD::VQSHLu; break;
8120 VShiftOpc = ARMISD::VQSHLsu; break;
8122 VShiftOpc = ARMISD::VQSHRNs; break;
8124 VShiftOpc = ARMISD::VQSHRNu; break;
8126 VShiftOpc = ARMISD::VQSHRNsu; break;
8128 VShiftOpc = ARMISD::VQRSHRNs; break;
8130 VShiftOpc = ARMISD::VQRSHRNu; break;
8132 VShiftOpc = ARMISD::VQRSHRNsu; break;
8145 VShiftOpc = ARMISD::VSLI;
8147 VShiftOpc = ARMISD::VSRI;
8200 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
8208 ARMISD::VSHRs : ARMISD::VSHRu);
8242 Opc = ARMISD::VGETLANEs;
8246 Opc = ARMISD::VGETLANEu;
8310 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
8332 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
8341 /// PerformCMOVCombine - Target-specific DAG combining for ARMISD::CMOV.
8345 if (Cmp.getOpcode() != ARMISD::CMPZ)
8378 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, TrueVal, ARMcc,
8383 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, FalseVal, ARMcc,
8415 case ARMISD::BFI: return PerformBFICombine(N, DCI);
8416 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
8417 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
8422 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI);
8434 case ARMISD::CMOV: return PerformCMOVCombine(N, DCI.DAG);
8435 case ARMISD::VLD2DUP:
8436 case ARMISD::VLD3DUP:
8437 case ARMISD::VLD4DUP:
8914 case ARMISD::CMOV: {
