Lines Matching refs:BUILD_VECTOR
120 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
554 setTargetDAGCombine(ISD::BUILD_VECTOR);
987 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
4179 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], NumElts);
4203 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
4213 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
4497 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
4501 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
4531 // Test if V1 is a BUILD_VECTOR which is equivalent to a SCALAR_TO_VECTOR
4534 if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR &&
4632 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
4690 /// isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each
4695 // A v2i64 BUILD_VECTOR will have been legalized to a BITCAST from v4i32.
4700 BVN->getOpcode() != ISD::BUILD_VECTOR)
4721 if (N->getOpcode() != ISD::BUILD_VECTOR)
4745 /// or a constant BUILD_VECTOR with sign-extended elements.
4755 /// or a constant BUILD_VECTOR with zero-extended elements.
4765 /// load, or BUILD_VECTOR with extended elements, return the unextended value.
4774 // Otherwise, the value must be a BUILD_VECTOR. For v2i64, it will
4778 assert(BVN->getOpcode() == ISD::BUILD_VECTOR &&
4779 BVN->getValueType(0) == MVT::v4i32 && "expected v4i32 BUILD_VECTOR");
4781 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), MVT::v2i32,
4784 // Construct a new BUILD_VECTOR with elements truncated to half the size.
4785 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
4796 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
4916 Y = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Y, Y, Y, Y);
4952 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
5061 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
5175 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
6718 || N0.getOpcode() != ISD::BUILD_VECTOR
6719 || N1.getOpcode() != ISD::BUILD_VECTOR)
6728 // N0 and N1 are BUILD_VECTOR nodes with N number of EXTRACT_VECTOR
7487 /// hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node
7502 /// ISD::BUILD_VECTOR.
7505 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X):
7531 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, FloatVT, Ops.data(), NumElts);
7909 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
7945 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
7957 /// Getvshiftimm - Check if this is a valid build_vector for the immediate
7959 /// build_vector must have the same constant integer value.
7976 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
7988 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
8419 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI);
