Lines Matching refs:VMOVRRD
727 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
794 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
921 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
1268 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1898 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
1915 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1953 } else if (Copy->getOpcode() == ARMISD::VMOVRRD) {
3267 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
3283 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
3331 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
3356 // Turn f64->i64 into VMOVRRD.
3358 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
7288 /// ARMISD::VMOVRRD.
7291 // vmovrrd(vmovdrr x, y) -> x,y
7296 // vmovrrd(load f64) -> (load i32), (load i32)
7333 // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X)
7340 if (Op0.getOpcode() == ARMISD::VMOVRRD &&
7505 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X):
7506 // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value
7508 // but if the i64 value is converted to a vector, we need to undo the VMOVRRD.
8416 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
