Lines Matching full:i128
109 addRegisterClass(MVT::i128, SPU::GPRCRegisterClass);
119 setTruncStoreAction(MVT::i128, MVT::i64, Expand);
120 setTruncStoreAction(MVT::i128, MVT::i32, Expand);
121 setTruncStoreAction(MVT::i128, MVT::i16, Expand);
122 setTruncStoreAction(MVT::i128, MVT::i8, Expand);
131 for (unsigned sctype = (unsigned) MVT::i8; sctype < (unsigned) MVT::i128;
200 setOperationAction(ISD::SREM, MVT::i128, Expand);
201 setOperationAction(ISD::UREM, MVT::i128, Expand);
202 setOperationAction(ISD::SDIV, MVT::i128, Expand);
203 setOperationAction(ISD::UDIV, MVT::i128, Expand);
204 setOperationAction(ISD::SDIVREM, MVT::i128, Expand);
205 setOperationAction(ISD::UDIVREM, MVT::i128, Expand);
288 setOperationAction(ISD::CTPOP, MVT::i128, Expand);
294 setOperationAction(ISD::CTTZ , MVT::i128, Expand);
299 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i128, Expand);
305 setOperationAction(ISD::CTLZ , MVT::i128, Expand);
310 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i128, Expand);
325 // Custom lower i128 -> i64 truncates
328 // Custom lower i32/i64 -> i128 sign extend
329 setOperationAction(ISD::SIGN_EXTEND, MVT::i128, Custom);
341 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Expand);
342 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Expand);
667 // Do the load as a i128 to allow possible shifting
668 SDValue low = DAG.getLoad(MVT::i128, dl, the_chain, basePtr,
679 result = DAG.getNode(SPUISD::ROTBYTES_LEFT, dl, MVT::i128,
700 ones = DAG.getNode(ISD::BITCAST, dl, MVT::i128, ones);
702 SDValue high = DAG.getLoad(MVT::i128, dl, the_chain,
716 high = DAG.getNode(SPUISD::SRL_BYTES, dl, MVT::i128, high,
724 low = DAG.getNode(SPUISD::SHL_BYTES, dl, MVT::i128, low, offset );
728 DAG.getNode(ISD::OR, dl, MVT::i128, low, high));
930 ones = DAG.getNode(ISD::BITCAST, dl, MVT::i128, ones);
941 lowmask = DAG.getNode(SPUISD::SRL_BYTES, dl, MVT::i128, ones, surplus);
942 lowmask = DAG.getNode(SPUISD::SHL_BYTES, dl, MVT::i128, lowmask,
944 Value = DAG.getNode(ISD::BITCAST, dl, MVT::i128, Value);
945 Value = DAG.getNode(ISD::AND, dl, MVT::i128, Value, lowmask);
950 Value = DAG.getNode(ISD::BITCAST, dl, MVT::i128, Value);
953 himask = DAG.getNode(SPUISD::SHL_BYTES, dl, MVT::i128, lowmask,
955 lowmask = DAG.getNode(SPUISD::SRL_BYTES, dl, MVT::i128, lowmask,
960 SDValue hi = DAG.getLoad(MVT::i128, dl, the_chain,
969 low = DAG.getNode(ISD::AND, dl, MVT::i128,
970 DAG.getNode( ISD::BITCAST, dl, MVT::i128, low),
971 DAG.getNode( ISD::XOR, dl, MVT::i128, lowmask, ones));
972 hi = DAG.getNode(ISD::AND, dl, MVT::i128,
973 DAG.getNode( ISD::BITCAST, dl, MVT::i128, hi),
974 DAG.getNode( ISD::XOR, dl, MVT::i128, himask, ones));
978 SDValue rlow = DAG.getNode(SPUISD::SRL_BYTES, dl, MVT::i128, Value, offset);
979 rlow = DAG.getNode(ISD::AND, dl, MVT::i128, rlow, lowmask);
980 SDValue rhi = DAG.getNode(SPUISD::SHL_BYTES, dl, MVT::i128, Value,
985 rlow = DAG.getNode(ISD::OR, dl, MVT::i128,
986 DAG.getNode(ISD::BITCAST, dl, MVT::i128, low),
987 DAG.getNode(ISD::BITCAST, dl, MVT::i128, rlow));
988 rhi = DAG.getNode(ISD::OR, dl, MVT::i128,
989 DAG.getNode(ISD::BITCAST, dl, MVT::i128, hi),
990 DAG.getNode(ISD::BITCAST, dl, MVT::i128, rhi));
1166 case MVT::i128:
1323 case MVT::i128:
2681 if (Op0VT == MVT::i128 && simpleVT == MVT::i64) {
2702 * Emit the instruction sequence for i64/i32 -> i128 sign extend. The basic
2728 // The type to extend to needs to be a i128 and
2730 assert((OpVT == MVT::i128 && (Op0VT == MVT::i64 || Op0VT == MVT::i32)) &&
2753 // reinterpret as a i128 (SHUFB requires it). This gets lowered away.
2763 return DAG.getNode(ISD::BITCAST, dl, MVT::i128, extShuffle);
