Lines Matching refs:v16i8
400 addRegisterClass(MVT::v16i8, SPU::VECREGRegisterClass);
452 setOperationAction(ISD::AND, MVT::v16i8, Custom);
453 setOperationAction(ISD::OR, MVT::v16i8, Custom);
454 setOperationAction(ISD::XOR, MVT::v16i8, Custom);
550 %1 v16i8,ch = load
551 %2 v16i8,ch = rotate %1
682 // Convert the loaded v16i8 vector to the appropriate vector type
1180 case MVT::v16i8:
1234 SDValue ArgVal = DAG.getRegister(VReg, MVT::v16i8);
1331 case MVT::v16i8:
1596 /// @note: The incoming vector is v16i8 because that's the only way we can load
1696 case MVT::v16i8: {
1857 maskVT = MVT::v16i8;
1944 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
1967 case MVT::v16i8: n_copies = 16; VT = MVT::i8; break;
2293 //! Lower byte immediate operations for v16i8 vectors:
