Lines Matching refs:MachineInstr
68 unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
98 unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
148 MachineInstr *Term = MBB.getFirstTerminator();
216 MachineInstr *LastInst = I;
242 MachineInstr *SecondLastInst = I;
396 SmallVectorImpl<MachineInstr*> &NewMIs) const
437 SmallVectorImpl<MachineInstr*> &NewMIs) const {
442 MachineInstr *HexagonInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
443 MachineInstr* MI,
471 bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
1255 PredicateInstruction(MachineInstr *MI,
1320 bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const {
1328 HexagonInstrInfo::DefinesPredicate(MachineInstr *MI,
1374 bool HexagonInstrInfo::isDeallocRet(const MachineInstr *MI) const {
1528 isMemOp(const MachineInstr *MI) const {
1580 isSpillPredRegOp(const MachineInstr *MI) const {
1591 bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const {
1631 isConditionalLoad (const MachineInstr* MI) const {
1710 bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
