Lines Matching refs:VA
721 CCValAssign &VA = ArgLocs[i];
722 MVT RegVT = VA.getLocVT();
726 switch (VA.getLocInfo()) {
742 if (VA.isRegLoc()) {
743 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
746 assert(VA.isMemLoc());
754 unsigned ArgSize = VA.getValVT().getSizeInBits()/8;
755 unsigned StackLoc = VA.getLocMemOffset() + 4;
893 CCValAssign &VA = ArgLocs[i];
896 if (VA.isRegLoc()) {
897 MVT RegVT = VA.getLocVT();
898 ArgRegEnd = VA.getLocReg();
917 if (VA.getLocInfo() != CCValAssign::Full) {
919 if (VA.getLocInfo() == CCValAssign::SExt)
921 else if (VA.getLocInfo() == CCValAssign::ZExt)
925 DAG.getValueType(VA.getValVT()));
926 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
930 } else { // VA.isRegLoc()
932 assert(VA.isMemLoc());
945 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
946 unsigned StackLoc = VA.getLocMemOffset() + 4;
953 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
1036 CCValAssign &VA = RVLocs[i];
1037 assert(VA.isRegLoc() && "Can only return in registers!");
1039 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
