Lines Matching refs:loop
255 // simple loop. The incoming instruction knows the destination vreg to
265 // loop:
268 // bneid samt, loop
273 MachineBasicBlock *loop = F->CreateMachineBasicBlock(LLVM_BB);
275 F->insert(It, loop);
287 MBB->addSuccessor(loop);
290 // Next, add the finish block as a successor of the loop block
291 loop->addSuccessor(finish);
292 loop->addSuccessor(loop);
310 BuildMI(loop, dl, TII->get(MBlaze::PHI), DST)
312 .addReg(NDST).addMBB(loop);
316 BuildMI(loop, dl, TII->get(MBlaze::PHI), SAMT)
318 .addReg(NAMT).addMBB(loop);
321 BuildMI(loop, dl, TII->get(MBlaze::ADD), NDST).addReg(DST).addReg(DST);
323 BuildMI(loop, dl, TII->get(MBlaze::SRA), NDST).addReg(DST);
325 BuildMI(loop, dl, TII->get(MBlaze::SRL), NDST).addReg(DST);
329 BuildMI(loop, dl, TII->get(MBlaze::ADDIK), NAMT)
333 BuildMI(loop, dl, TII->get(MBlaze::BNEID))
335 .addMBB(loop);
340 .addReg(NDST).addMBB(loop);
435 // simple loop. The incoming instruction knows the destination vreg to
445 // loop:
448 // bneid samt, loop
